欢迎访问ic37.com |
会员登录 免费注册
发布采购

UC3844BD1R2G 参数 Datasheet PDF下载

UC3844BD1R2G图片预览
型号: UC3844BD1R2G
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能电流模式控制器 [HIGH PERFORMANCE CURRENT MODE CONTROLLERS]
分类和应用: 稳压器开关式稳压器或控制器电源电路开关式控制器光电二极管
文件页数/大小: 20 页 / 320 K
品牌: ONSEMI [ ONSEMI ]
 浏览型号UC3844BD1R2G的Datasheet PDF文件第6页浏览型号UC3844BD1R2G的Datasheet PDF文件第7页浏览型号UC3844BD1R2G的Datasheet PDF文件第8页浏览型号UC3844BD1R2G的Datasheet PDF文件第9页浏览型号UC3844BD1R2G的Datasheet PDF文件第11页浏览型号UC3844BD1R2G的Datasheet PDF文件第12页浏览型号UC3844BD1R2G的Datasheet PDF文件第13页浏览型号UC3844BD1R2G的Datasheet PDF文件第14页  
UC3844B, UC3845B, UC2844B, UC2845B  
Undervoltage Lockout  
designer added flexibility in tailoring the drive voltage  
Two undervoltage lockout comparators have been  
incorporated to guarantee that the IC is fully functional  
before the output stage is enabled. The positive power  
supply terminal (V ) and the reference output (V ) are  
each monitored by separate comparators. Each has built−in  
hysteresis to prevent erratic output behavior as their  
independent of V . A Zener clamp is typically connected  
to this input when driving power MOSFETs in systems  
CC  
where V is greater than 20 V. Figure 23 shows proper  
CC  
power and control ground connections in a current−sensing  
power MOSFET application.  
CC  
ref  
Reference  
respective thresholds are crossed. The V  
comparator  
CC  
The 5.0 V bandgap reference is trimmed to ±1.0%  
upper and lower thresholds are 16 V/10 V for the UCX844B,  
tolerance at T = 25°C on the UC284XB, and ±2.0% on the  
J
and 8.4 V/7.6 V for the UCX845B. The V comparator  
ref  
UC384XB. Its primary purpose is to supply charging current  
to the oscillator timing capacitor. The reference has  
short−circuit protection and is capable of providing in  
excess of 20 mA for powering additional control system  
circuitry.  
upper and lower thresholds are 3.6 V/3.4 V. The large  
hysteresis and low startup current of the UCX844B makes  
it ideally suited in off−line converter applications where  
efficient bootstrap startup techniques are required  
(Figure 30). The UCX845B is intended for lower voltage  
dc−dc converter applications. A 36 V Zener is connected as  
Design Considerations  
a shunt regulator from V to ground. Its purpose is to  
CC  
Do not attempt to construct the converter on  
wire−wrap or plug−in prototype boards. High frequency  
circuit layout techniques are imperative to prevent  
pulse−width jitter. This is usually caused by excessive noise  
pick−up imposed on the Current Sense or Voltage Feedback  
inputs. Noise immunity can be improved by lowering circuit  
impedances at these points. The printed circuit layout should  
contain a ground plane with low−current signal and  
high−current switch and output grounds returning on  
separate paths back to the input filter capacitor. Ceramic  
protect the IC from excessive voltage that can occur during  
system startup. The minimum operating voltage for the  
UCX844B is 11 V and 8.2 V for the UCX845B.  
Output  
These devices contain a single totem pole output stage that  
was specifically designed for direct drive of power  
MOSFETs. It is capable of up to ±1.0 A peak drive current  
and has a typical rise and fall time of 50 ns with a 1.0 nF load.  
Additional internal circuitry has been added to keep the  
Output in a sinking mode whenever an undervoltage lockout  
is active. This characteristic eliminates the need for an  
external pulldown resistor.  
bypass capacitors (0.1 mF) connected directly to V , V ,  
CC  
C
and V may be required depending upon circuit layout.  
ref  
This provides a low impedance path for filtering the high  
frequency noise. All high current loops should be kept as  
short as possible using heavy copper runs to minimize  
radiated EMI. The Error Amp compensation circuitry and  
the converter output voltage divider should be located close  
to the IC and as far as possible from the power switch and  
other noise−generating components.  
The SOIC−14 surface mount package provides separate  
pins for V (output supply) and Power Ground. Proper  
C
implementation will significantly reduce the level of  
switching transient noise imposed on the control circuitry.  
This becomes particularly useful when reducing the I  
pk(max)  
clamp level. The separate V supply input allows the  
C
V
ref  
8(14)  
8(14)  
R
R
R
R
A
B
Bias  
Bias  
R
T
R
8
4
R
5.0k  
5.0k  
6
3
7
Osc  
2R  
Osc  
4(7)  
4(7)  
C
R
S
T
+
+
5
2
Q
0.01  
2R  
External  
Sync  
Input  
EA  
R
EA  
R
2(3)  
1(1)  
2(3)  
1(1)  
5.0k  
1
47  
C
MC1455  
5(9)  
5(9)  
To Additional  
UCX84XBs  
The diode clamp is required if the Sync amplitude is large enough to cause  
the bottom side of C to go more than 300 mV below ground.  
1.44  
(R ꢁ )ꢁ 2R )C  
R
A
fꢁ +ꢁ  
D
(max)  
+ꢁ  
T
R ꢁ )ꢁ 2R  
A B  
A
B
Figure 18. External Clock Synchronization  
Figure 19. External Duty Cycle Clamp and  
Multi−Unit Synchronization  
http://onsemi.com  
10  
 复制成功!