UC3842A, 43A UC2842A, 43A
Figure 21. External Duty Cycle Clamp and
Multi Unit Synchronization
Figure 20. External Clock Synchronization
V
ref
8(14)
R
R
8(14)
R
Bias
R
R
A
R
T
Bias
4
8
R
B
5.0k
6
Osc
+
External
Sync
Input
Osc
+
4(7)
R
S
–
C
T
3
0.01
+
4(7)
5
2
Q
+
–
+
–
+
–
2R
R
7
EA
47
2(3)
1(1)
2R
R
5.0k
1
EA
2(3)
1(1)
C
MC1455
5(9)
5(9)
To Additional
UCX84XA’s
R
B
1.44
(R + 2R )C
The diode clamp is required if the Sync amplitude is large enough to
cause the bottom side of CT to go more than 300 mV below ground.
f =
D
=
max
R
+ 2R
B
A
B
A
Figure 22. Adjustable Reduction of Clamp Level
Figure 23. Soft–Start Circuit
V
CC
V
in
7(12)
5.0V
+
ref
5.0V
ref
–
8(14)
R
R
+
8(14)
R
R
Bias
+
–
–
Bias
+
+
–
+
7(11)
6(10)
5(8)
–
–
Q1
Osc
Osc
+
4(7)
2(3)
+
4(7)
V
Clamp
S
R
1.0mA
2R
+
–
1.0mA
2R
S
R
Q
–
+
–
Q
–
+
R2
EA
+
EA
2(3)
1(1)
R
1.0M
Comp/Latch
R
1.0V
1.0V
3(5)
1(1)
t
C
R
S
R1
5(9)
5(9)
3600C in µF
Soft–Start
1.67
2
R
R
2
1
VClamp
RS
V
=
+ 0.33 x 10 –
3
I =
pk(max)
Clamp
R
+ R
1
2
R
R
+ 1
Where: 0
≤
V
≤
1.0 V
Clamp
1
Figure 24. Adjustable Buffered Reduction of
Figure 25. Current Sensing Power MOSFET
Clamp Level with Soft–Start
V
CC
R
I
r
S
pk DS(on)
+ R
V
V
in
CC
V
5 =
V
(12)
Pin
in
r
DM(on)
S
7(12)
If: SENSEFET = MTP10N10M
+
–
R
= 200
5.0V
ref
S
+
+
5.0V
ref
–
Then: V
SENSEFET
5 = 0.075 I
pk
+
pin
8(14)
4(7)
R
R
–
+
D
–
Bias
–
+
+
–
(11)
(10)
(8)
+
S
7(11)
6(10)
5(8)
–
–
Q1
Osc
G
K
M
+
V
Clamp
S
R
S
R
Q
1.0mA
2R
–
+
–
Q
+
–
Power Ground
To Input Source
Return
+
Comp/Latch
EA
2(3)
1(1)
Comp/Latch
R
R2
(5)
R
1.0V
3(5)
S
1/4 W
R
S
Control CIrcuitry
Ground:
5(9)
MPSA63
C
To Pin (9)
R1
1.67
2
VClamp
RS
V
=
Clamp
I
=
Where: 0
V
≤
V
≤ 1.0 V
pk(max)
Clamp
C
R
R
Virtually lossless current sensing can be achieved with the implementation of
SENSEFET power switch. For proper operation during over current conditions, a
reduction of the I clamp level must be implemented. Refer to Figures 22 and 24.
a
+ 1
R
R
2
C
1
1
t
= – In
1 –
Softstart
3V
Clamp
R
+ R
1 2
pk(max)
11
MOTOROLA ANALOG IC DEVICE DATA
ONSEMI [ ONSEMI ]
