UC3842A, UC3843A, UC2842A, UC2843A
V
ref
8(14)
R
8(14)
4(7)
R
R
Bias
R
A
R
T
R
Bias
4
8
R
B
5.0k
6
Osc
+
−
External
Sync
Input
Osc
+
4(7)
R
S
C
T
3
0.01
+
5
2
Q
+
+
−
−
+
2R
7
EA
47
−
2(3)
1(1)
2R
R
5.0k
1
EA
2(3)
1(1)
C
MC1455
R
5(9)
5(9)
To
Additional
UCX84XA’s
R
B
1.44
(R + 2R )C
The diode clamp is required if the Sync amplitude is large enough to
cause the bottom side of CT to go more than 300 mV below ground.
f =
D
max
=
R
A
+ 2R
B
A
B
Figure 22. External Duty Cycle Clamp and
Multi Unit Synchronization
Figure 21. External Clock Synchronization
V
CC
V
in
7(12)
+
5.0V
ref
−
+
8(14)
4(7)
R
R
−
Bias
+
−
+
7(11)
6(10)
5(8)
5.0V
ref
−
Q1
8(14)
R
R
Osc
Bias
+
+
V
−
Clamp
+
1.0mA
2R
S
R
+
−
Q
−
−
R2
+
Osc
EA
2(3)
1(1)
Comp/Latch
R
+
4(7)
2(3)
1.0V
3(5)
S
R
1.0mA
2R
+
Q
−
R
S
−
R1
+
EA
5(9)
R
1.0M
1.0V
1.67
2
R
R
2
1(1)
t
1
VClamp
RS
C
V
=
+ 0.33 x 10 −
3
I
=
Clamp
pk(max)
R
+ R
2
1
R
R
5(9)
+ 1
ꢀ 3600C in ꢀF
Soft−Start
Where: 0 ≤ V
≤ 1.0 V
Clamp
1
Figure 23. Adjustable Reduction of Clamp Level
Figure 24. Soft−Start Circuit
V
CC
R
I
r
pk DS(on)
S
V
in
V
CC
V
5 =
Pin
V
in
(12)
r
+ R
S
DM(on)
7(12)
If: SENSEFET = MTP10N10M
= 200
+
R
S
5.0V
−
+
ref
+
5.0V
ref
−
Then: V 5 = 0.075 I
pin
+
pk
8(14)
4(7)
R
R
−
+
D
SENSEFET
−
Bias
−
+
+
−
(11)
(10)
(8)
+
S
7(11)
6(10)
5(8)
−
−
Q1
Osc
G
K
M
+
V
Clamp
S
R
S
R
Q
1.0mA
2R
−
+
Q
+
−
−
Power Ground
To Input Source
Return
+
Comp/Latch
EA
2(3)
1(1)
Comp/Latch
R
R2
(5)
R
1.0V
S
3(5)
1/4 W
R
S
Control CIrcuitry
Ground:
To Pin (9)
5(9)
=
MPSA63
C
R1
1.67
2
VClamp
RS
V
=
Clamp
I
Where: 0 ≤ V
≤ 1.0 V
pk(max)
Clamp
R
R
Virtually lossless current sensing can be achieved with the implementation of a
SENSEFET power switch. For proper operation during over current conditions, a
+ 1
V
R R
1 2
C
1
t
= − In
1 −
C
Softstart
3V
R + R
1 2
reduction of the I
clamp level must be implemented. Refer to Figures 23 and 25.
Clamp
pk(max)
Figure 25. Adjustable Buffered Reduction of
Clamp Level with Soft−Start
Figure 26. Current Sensing Power MOSFET
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