SN54/74LS390
•
SN54/74LS393
PIN NAMES
CP
CP0
CP1
MR
Q0 – Q3
Clock (Active LOW going edge)
Input to +16 (LS393)
Clock (Active LOW going edge)
Input to
÷
2 (LS390)
Clock (Active LOW going edge)
Input to
÷
5 (LS390)
Master Reset (Active HIGH) Input
Flip-Flop outputs (Note b)
LOADING
(Note a)
HIGH
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
LOW
1.0 U.L.
1.0 U.L.
1.5 U.L.
0.25 U.L.
5 (2.5) U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40
µA
HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b)
Temperature Ranges.
FUNCTIONAL DESCRIPTION
Each half of the SN54 / 74LS393 operates in the Modulo 16
binary sequence, as indicated in the
÷
16 Truth Table. The first
flip-flop is triggered by HIGH-to-LOW transitions of the CP
input signal. Each of the other flip-flops is triggered by a
HIGH-to-LOW transition of the Q output of the preceding
flip-flop. Thus state changes of the Q outputs do not occur
simultaneously. This means that logic signals derived from
combinations of these outputs will be subject to decoding
spikes and, therefore, should not be used as clocks for other
counters, registers or flip-flops. A HIGH signal on MR forces
all outputs to the LOW state and prevents counting.
Each half of the LS390 contains a
÷
5 section that is
independent except for the common MR function. The
÷
5
section operates in 4.2.1 binary sequence, as shown in the
÷
5
Truth Table, with the third stage output exhibiting a 20% duty
cycle when the input frequency is constant. To obtain a
÷10
function having a 50% duty cycle output, connect the input
signal to CP1 and connect the Q3 output to the CP0 input; the
Q0 output provides the desired 50% duty cycle output. If the
input frequency is connected to CP0 and the Q0 output is
connected to CP1, a decade divider operating in the 8.4.2.1
BCD code is obtained, as shown in the BCD Truth Table. Since
the flip-flops change state asynchronously, logic signals
derived from combinations of LS390 outputs are also subject
to decoding spikes. A HIGH signal on MR forces all outputs
LOW and prevents counting.
SN54 / 74LS390 LOGIC DIAGRAM (one half shown)
CP1
CP0
K CP
CD
MR
J
Q
CD
K CP
J
Q
CD
K CP
J
Q
CD
K CP
J
Q
Q0
Q1
Q2
Q3
SN54 / 74LS393 LOGIC DIAGRAM (one half shown)
CP
K CP
CD
MR
J
Q
CD
K CP
J
Q
CD
K CP
J
Q
CD
K CP
J
Q
Q0
Q1
Q2
Q3
FAST AND LS TTL DATA
5-2
ONSEMI [ ON SEMICONDUCTOR ]
