SN74LS175
AC CHARACTERISTICS
(T
A
= 25°C)
Limits
Symbol
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
Parameter
Maximum Input Clock Frequency
Propagation Delay, MR to Output
Propagation Delay, Clock to Output
Min
30
Typ
40
20
20
13
16
30
30
25
25
Max
Unit
MHz
ns
ns
V
CC
= 5.0 V
C
L
= 15 pF
F
Test Conditions
AC SETUP REQUIREMENTS
(T
A
= 25°C)
Limits
Symbol
t
W
t
s
t
h
t
rec
Parameter
Clock or MR Pulse Width
Data Setup Time
Data Hold Time
Recovery Time
Min
20
20
5.0
25
Typ
Max
Unit
ns
ns
ns
ns
V
CC
= 5 0 V
5.0
Test Conditions
AC WAVEFORMS
1/f
max
CP
1.3 V
t
s(H)
D
*
1.3 V
t
h(H)
t
s(L)
t
w
1.3 V
t
h(L)
1.3 V
t
PHL
1.3 V
t
PLH
1.3 V
Q
CP
Q
t
PLH
1.3 V
1.3 V
t
PHL
1.3 V
1.3 V
MR
1.3 V
t
W
1.3 V
t
rec
1.3 V
1.3 V
t
PLH
1.3 V
t
PHL
1.3 V
Q
Q
*The shaded areas indicate when the input is permitted to
*change
for predictable output performance.
Figure 1. Clock to Output Delays, Clock Pulse Width,
Frequency, Setup and Hold Times Data to Clock
Figure 2. Master Reset to Output Delay, Master Reset
Pulse Width, and Master Reset Recovery Time
DEFINITIONS OF TERMS
SETUP TIME (t
s
) — is defined as the minimum time
required for the correct logic level to be present at the logic
input prior to the clock transition from LOW to HIGH in
order to be recognized and transferred to the outputs.
HOLD TIME (t
h
) — is defined as the minimum time
following the clock transition from LOW to HIGH that the
logic level must be maintained at the input in order to ensure
continued recognition. A negative HOLD TIME indicates
that the correct logic level may be released prior to the clock
transition from LOW to HIGH and still be recognized.
RECOVERY TIME (t
rec
) — is defined as the minimum time
required between the end of the reset pulse and the clock
transition from LOW to HIGH in order to recognize and
transfer HIGH Data to the Q outputs.
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