SA572
Audio Signal Processing IC Combines VCA and
Fast Attack/Slow Recovery Level Sensor
In high-performance audio gain control applications, it
is desirable to independently control the attack and
recovery time of the gain control signal. This is true, for
example, in compandor applications for noise reduction. In
high end systems the input signal is usually split into two
or more frequency bands to optimize the dynamic behavior
for each band. This reduces low frequency distortion due
to control signal ripple, phase distortion, high frequency
channel overload and noise modulation. Because of the
expense in hardware, multiple band signal processing up to
now was limited to professional audio applications.
With the introduction of the SA572 this high-
performance noise reduction concept becomes feasible for
consumer hi fi applications. The SA572 is a dual channel
gain control IC. Each channel has a linearized,
temperature-compensated gain cell and an improved level
sensor. In conjunction with an external low noise op amp
for current-to-voltage conversion, the VCA features low
distortion, low noise and wide dynamic range.
The novel level sensor which provides gain control
current for the VCA gives lower gain control ripple and
independent control of fast attack, slow recovery dynamic
response. An attack capacitor C
A
with an internal 10 kW
resistor R
A
defines the attack time
t
A
. The recovery time
t
R
of a tone burst is defined by a recovery capacitor C
R
and
an internal 10 kW resistor R
R
. Typical attack time of 4.0 ms
for the high-frequency spectrum and 40 ms for the low
frequency band can be obtained with 0.1
mF
and 1.0
mF
attack capacitors, respectively. Recovery time of 200 ms
can be obtained with a 4.7
mF
recovery capacitor for a
100 Hz signal, the third harmonic distortion is improved by
more than 10 dB over the simple RC ripple filter with a
single 1.0
mF
attack and recovery capacitor, while the
attack time remains the same.
The SA572 is assembled in a standard 16-pin dual in-line
plastic package and in oversized SOL package. It operates
over a wide supply range from 6.0 V to 22 V. Supply
current is less than 6.0 mA. The SA572 is designed for
applications from
−40°C
to +85°C.
BASIC APPLICATIONS
Description
The SA572 consists of two linearized, temperature-
compensated gain cells (DG), each with a full-wave
rectifier and a buffer amplifier as shown in the block
diagram. The two channels share a 2.5 V common bias
reference derived from the power supply but otherwise
operate independently. Because of inherent low distortion,
low noise and the capability to linearize large signals, a
wide dynamic range can be obtained. The buffer amplifiers
are provided to permit control of attack time and recovery
time independent of each other. Partitioned as shown in the
block diagram, the IC allows flexibility in the design of
system levels that optimize DC shift, ripple distortion,
tracking accuracy and noise floor for a wide range of
application requirements.
Gain Cell
V
T
I
n
1
I
2 G
)
1
I
O
2
*
V
T
I
n
I
S
1I
*
1I
2
G
2
O
I
S
(eq. 1)
+
V
T
I
n
I
2
*
I
1
*
I
IN
I
1
)
I
IN
*
V
T
I
n
I
S
I
S
where I
IN
+
V
IN
R
1
R
1
= 6.8 kW
I
1
= 140
mA
I
2
= 280
mA
I
O
is the differential output current of the gain cell and I
G
is the gain control current of the gain cell.
If all transistors Q
1
through Q
4
are of the same size,
equation 1 can be simplified to:
I
O
+
2
@
I
IN
@
I
G
*
1 I
2
*
2I
1
@
I
G
I
2
I
2
(eq. 2)
Figure 3 shows the circuit configuration of the gain cell.
Bases of the differential pairs Q
1
-Q
2
and Q
3
-Q
4
are both
tied to the output and inputs of OPA A
1
. The negative
feedback through Q
1
holds the V
BE
of Q
1
-Q
2
and the V
BE
of Q
3
-Q
4
equal. The following relationship can be derived
from the transistor model equation in the forward active
region.
DV
BE
Q3Q4
+
D
BE
Q1Q2
(V
BE
= V
T
I
IN
IC/IS)
The first term of equation 2 shows the multiplier
relationship of a linearized two quadrant transconductance
amplifier. The second term is the gain control feedthrough
due to the mismatch of devices. In the design, this has been
minimized by large matched devices and careful layout.
Offset voltage is caused by the device mismatch and it leads
to even harmonic distortion. The offset voltage can be
trimmed out by feeding a current source within
"25
mA
into the THD trim pin.
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