MC3456
Control Voltage
Threshold
Comparator
V
CC
4.7 k
830
4.7 k
Trigger
Comparator
1.0 k
Flip−Flop
Output
6.8 k
5.0 k
Threshold
7.0 k
10 k
c
5.0 k
Trigger
Reset
Reset
Discharge
Gnd
Discharge
100
100 k
5.0 k
220
4.7 k
cb
e
4.7 k
b
3.9 k
Output
Figure 13. 1/2 Representative Circuit Schematic
GENERAL OPERATION
The MC3456 is a dual timing circuit which uses as its
timing elements an external resistor/capacitor network. It
can be used in both the monostable (one shot) and astable
modes with frequency and duty cycle, controlled by the
capacitor and resistor values. While the timing is dependent
upon the external passive components, the monolithic
circuit provides the starting circuit, voltage comparison and
other functions needed for a complete timing circuit.
Internal to the integrated circuit are two comparators, one for
the input signal and the other for capacitor voltage; also a
flip−flop and digital output are included. The comparator
reference voltages are always a fixed ratio of the supply
voltage thus providing output timing independent of supply
voltage.
Monostable Mode
In the monostable mode, a capacitor and a single resistor
are used for the timing network. Both the threshold terminal
and the discharge transistor terminal are connected together
in this mode (refer to circuit Figure 15). When the input
voltage to the trigger comparator falls below 1/3 V
CC
the
comparator output triggers the flip−flop so that it’s output
sets low. This turns the capacitor discharge transistor “off”
and drives the digital output to the high state. This condition
allows the capacitor to charge at an exponential rate which
is set by the RC time constant. When the capacitor voltage
reaches 2/3 V
CC
the threshold comparator resets the
flip−flop. This action discharges the timing capacitor and
returns the digital output to the low state. Once the flip−flop
has been triggered by an input signal, it cannot be retriggered
until the present timing period has been completed. The time
that the output is high is given by the equation t = 1.1 R
A
C.
Various combinations of R and C and their associated times
are shown in Figure 14. The trigger pulse width must be less
than the timing period.
A reset pin is provided to discharge the capacitor thus
interrupting the timing cycle. As long as the reset pin is low,
the capacitor discharge transistor is turned “on” and
prevents the capacitor from charging. While the reset
voltage is applied the digital output will remain the same.
The reset pin should be tied to the supply voltage when not
in use.
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