NCP5500, NCV5500, NCP5501, NCV5501
Calculating Resistors for the ADJ Versions
The adjustable version uses feedback resistors to adjust
the output to the desired output voltage. With V
out
connected
to ADJ, the adjustable version will regulate at 1.25 V
4.9%
(1250
61.25 mV).
Output voltage formula with an external resistor divider:
(R
1
@
R
2)
(R
1
)
R
2
)
(R1
)
R2)
R
2
Ripple Rejection:
The ratio of the peak−to−peak input ripple
voltage to the peak−to−peak output ripple voltage.
Current Limit:
Peak current that can be delivered to the
output.
Calculating Power Dissipation
The maximum power dissipation for a single output
regulator (Figure 21) is:
P
D(max)
+
V
in(max)
*
V
out(min)
I
out(max)
)
V
in(max)
I
GND
(eq. 1)
V
out
+
1.25 V
*
60E−9
@
@
Where
R
1
= value of the divider resistor connected between V
out
and ADJ,
R
2
= value of the divider resistor connected between ADJ
and GND,
The term “1.25 V” has a tolerance of
4.9%;
the term
“60E−9” can vary in the range 15E−9 to 60E−9.
For values of R
2
less than 15 KW, the term within brackets
( [ ] ) will evaluate to less than 1 mV and can be ignored. This
simplifies the output voltage formula to:
V
out
= 1.25 V * ((R1 + R2) / R2)) with a tolerance of
4.9%,
which is the tolerance of the 1.25 V output when delivering
up to 500 mA of output current.
DEFINITION OF TERMS
Where
V
in(max)
is the maximum input voltage,
V
out(min)
is the minimum output voltage,
I
out(max)
is the maximum output current for the application,
I
GND
is the ground current at I
out(max)
.
Once the value of P
D(max)
is known, the maximum
permissible value of R
qJA
can be calculated:
R
qJA
+
150
C
*
T
A
P
D
(eq. 2)
Dropout Voltage:
The input−to−output voltage differential
at which the circuit ceases to regulate against further
reduction input voltage. Measured when the output voltage
has dropped 2% relative to the value measured at nominal
input voltage. Dropout voltage is dependent upon load
current and junction temperature.
Input Voltage:
The DC voltage applied to the input
terminals with respect to ground.
Line Regulation:
The change in output voltage for a change
in the input voltage. The measurement is made under
conditions of low dissipation or by using pulse techniques
such that the average chip temperature is not significantly
affected.
Load Regulation:
The change in output voltage for a change
in load current at constant chip temperature. Pulse loading
techniques are employed such that the average chip
temperature is not significantly affected.
Quiescent and Ground Current:
The quiescent current is
the current which flows through the ground when the LDO
operates without a load on its output: internal IC operation,
bias, etc. When the LDO becomes loaded, this term is called
the Ground current. It is actually the difference between the
input current (measured through the LDO input pin) and the
output current.
The value of R
qJA
can then be compared with those in the
Thermal Characteristics table. Those packages with R
qJA
less than the calculated value in Equation 2 will keep the die
temperature below 150C.
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external heat
sink will be required.
Heat Sinks
A heat sink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Each material in the heat flow path between the IC and the
outside environment will have a thermal resistance. Like
series electrical resistances, these resistances are summed to
determine the value of R
qJA
:
R
qJA
+
R
qJC
)
R
qCS
)
R
qSA
(eq. 3)
where
R
qJC
is the junction−to−case thermal resistance,
R
qCS
is the case−to−heatsink thermal resistance,
R
qSA
is the heatsink−to−ambient thermal resistance.
R
qJC
appears in the Thermal Characteristics table. Like
R
qJA
, it too is a function of package type. R
qCS
and R
qSA
are
functions of the package type, heat sink and the interface
between them. These values appear in data sheets of heat
sink manufacturers.
Thermal, mounting, and heat sink considerations are
further discussed in ON Semiconductor Application Note
AN1040/D.
http://onsemi.com
9
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