NCP5007
Basically, the chip operates with two cycles:
flip−flop resets, the NMOS is deactivated and the current is
dumped into the load. Since the timing is application
dependent, the internal timer limits the Toff cycle to 320 ns
(typical), making sure the system operates in a continuous
mode to maximize the energy transfer.
Cycle #1 : time t1, the energy is stored into the inductor
Cycle #2 : time t2, the energy is dumped to the load
The POR signal sets the flip−flop and the first cycle takes
place. When the current hits the peak value, defined by the
error amplifier associated with the loop regulation, the
First Startup
Normal Operation
Ipeak
I
L
Iv
t1
t2
0 mA
t
t
t
Ids
0 mA
Io
0 mA
Figure 4. Basic DC−DC Operation
Based on the data sheet, the current flowing into the
inductor is bounded by two limits:
• Ipeak Value: Internally fixed to 350 mA typical
• Iv Value: Limited by the fixed Toff time built in the
chip (320 ns typical)
The system operates in a continuous mode as depicted in
Of course, from a practical stand point, the inductor must
be sized to cope with the peak current present in the circuit
to avoid saturation of the core. On top of that, the ferrite
material shall be capable to operate at high frequency
(1.0 MHz) to minimize the Foucault’s losses developed
during the cycles.
The operating frequency can be derived from the
Figure 4 and t & t times can be derived from basic
1
2
electrical parameters. Let V = Vo − V , rearranging
bat
equations. (Note: The equations are for theoretical analysis
only, they do not include the losses.)
Equation 1:
dI * L
E
di
dt
(eq. 5)
ton +
(eq. 1)
E + L *
Since toff is nearly constant (according to the 320 ns
typical time), the dI is constant for a given load and
inductance value. Rearranging Equation 5 yields:
Let E = V , then:
bat
(Ip * Iv) * L
(eq. 2)
(eq. 3)
t1 +
t2 +
Vbat
V*dt * L
L
(Ip * Iv) * L
Vo * Vbat
(eq. 6)
ton +
E
Let E = V , and Vopk = output peak voltage, then:
bat
Since t = 320 ns typical and Vo = 22 V maximum, then
2
(assuming a typical V = 3.0 V):
(Vopk * Vbat) * dt
bat
(eq. 7)
ton +
Vbat
t2 * (Vo * Vbat)
DI +
Finally, the operating frequency is:
L
(eq. 4)
1
(eq. 8)
F +
* 9
320e
* (22 * 3.0)
* 6
ton ) toff
DImax +
+ 276 mA
22e
The output power supplied by the NCP5007 is limited to
one watt: Figure 5 shows the maximum power that can be
delivered by the chip as a function of the input voltage.
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