NBXSBA007
OE
NC
1
2
3
6
5
4
V
DD
CLK
CLK
GND
Figure 2. Pin Connections (Top View)
Table 1. PIN DESCRIPTION
Pin No.
Symbol
I/O
Description
1
OE
LVTTL/LVCMOS
Control Input
Output Enable Pin. When left floating pin defaults to logic HIGH and output is active.
See OE pin description Table 2.
2
3
4
NC
GND
CLK
N/A
No Connect.
Power Supply
LVPECL Output
Ground 0 V
Non−Inverted Clock Output. Typically loaded with 50 W receiver termination resistor to
V
TT
= V − 2 V.
DD
5
6
CLK
LVPECL Output
Power Supply
Inverted Clock Output. Typically loaded with 50 W receiver termination resistor to
= V − 2 V.
V
TT
DD
V
DD
Positive power supply voltage. Voltage should not exceed 3.3 V 10%.
Table 2. OUTPUT ENABLE TRI−STATE FUNCTION
OE Pin
Open
Output Pins
Active
HIGH Level
LOW Level
Active
High Z
Table 3. ATTRIBUTES
Characteristic
Internal Default State Resistor
ESD Protection Human Body Model
Machine Model
Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test
1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
Value
170 kW
2 kV
200 V
Table 4. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Units
V
V
Positive Power Supply
LVPECL Output Current
GND = 0 V
4.6
DD
out
I
Continuous
Surge
25
50
mA
T
Operating Temperature Range
Storage Temperature Range
Wave Solder
−40 to +85
−55 to +120
260
°C
°C
°C
A
T
stg
T
sol
See Figure 5
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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