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MC74VHC1GT08DFT2 参数 Datasheet PDF下载

MC74VHC1GT08DFT2图片预览
型号: MC74VHC1GT08DFT2
PDF下载: 下载PDF文件 查看货源
内容描述: 2输入与门/ CMOS逻辑电平转换器 [2−Input AND Gate/CMOS Logic Level Shifter]
分类和应用: 转换器电平转换器栅极触发器逻辑集成电路光电二极管
文件页数/大小: 6 页 / 74 K
品牌: ONSEMI [ ON SEMICONDUCTOR ]
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MC74VHC1GT08
2−Input AND Gate/CMOS
Logic Level Shifter
The MC74VHC1GT08 is an advanced high speed CMOS 2−input
AND gate fabricated with silicon gate CMOS technology. It achieves
high speed operation similar to equivalent Bipolar Schottky TTL
while maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The device input is compatible with TTL−type input thresholds and
the output has a full 5 V CMOS level output swing. The input protection
circuitry on this device allows overvoltage tolerance on the input,
allowing the device to be used as a logic−level translator from 3 V
CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to 3 V
CMOS Logic while operating at the high−voltage power supply.
The MC74VHC1GT08 input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage. This
allows the MC74VHC1GT08 to be used to interface 5 V circuits to
3 V circuits. The output structures also provide protection when
V
CC
= 0 V. These input and output structures help prevent device
destruction caused by supply voltage − input/output voltage mismatch,
battery backup, hot insertion, etc.
Features
http://onsemi.com
MARKING
DIAGRAMS
5
1
SC−88A/SOT−353/SC−70
DF SUFFIX
CASE 419A
5
VT M
G
G
M
1
5
VT M
G
G
1
5
1
TSOP−5/SOT−23/SC−59
DT SUFFIX
CASE 483
High Speed: t
PD
= 3.5 ns (Typ) at V
CC
= 5 V
Low Power Dissipation: I
CC
= 1
mA
(Max) at T
A
= 25°C
TTL−Compatible Inputs: V
IL
= 0.8 V; V
IH
= 2 V
CMOS−Compatible Outputs: V
OH
> 0.8 V
CC
; V
OL
< 0.1 V
CC
@Load
Power Down Protection Provided on Inputs and Outputs
Balanced Propagation Delays
Pin and Function Compatible with Other Standard Logic Families
Chip Complexity: FETs = 64; Equivalent Gates = 15
Pb−Free Packages are Available
VT = Device Code
M
= Date Code*
G
= Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation and/or position may vary
depending upon manufacturing location.
PIN ASSIGNMENT
1
2
3
4
5
IN B
IN A
GND
OUT Y
V
CC
IN B
1
5
V
CC
FUNCTION TABLE
IN A
2
A
GND
3
4
OUT Y
L
L
H
H
Inputs
B
L
H
L
H
Output
Y
L
L
L
H
Figure 1. Pinout
(Top View)
IN A
IN B
&
OUT Y
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
Figure 2. Logic Symbol
©
Semiconductor Components Industries, LLC, 2007
1
February, 2007 − Rev. 10
Publication Order Number:
MC74VHC1GT08/D