MC74HC139A
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
V
DC Supply Voltage
(Referenced to GND)
ꢀ 0.5 to ꢁ 7.0
CC
V
DC Input Voltage
(Referenced to GND)
ꢀ 1.5 to V ꢁ 1.5
V
IN
CC
V
DC Output Voltage
(Referenced to GND) (Note 1)
ꢀ 0.5 to V
ꢁ 0.5
V
OUT
CC
I
DC Input Current, per Pin
DC Output Current, per Pin
ꢂ 20
ꢂ 25
ꢂ 50
ꢂ 50
mA
mA
mA
mA
_C
_C
_C
_C/W
IN
I
OUT
I
DC Supply Current, V Pin
CC
CC
I
DC Ground Current per Ground Pin
Storage Temperature Range
GND
T
ꢀ 65 to ꢁ 150
260
STG
T
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature Under Bias
Thermal Resistance
L
T
ꢁ
1
5
0
J
q
PDIP
SOIC
TSSOP
78
112
148
JA
P
Power Dissipation in Still Air at 85_C
PDIP
SOIC
TSSOP
750
500
450
mW
D
MSL
Moisture Sensitivity
Flammability Rating
ESD Withstand Voltage
Level 1
F
Oxygen Index: 30% − 35%
UL 94 V−0 @ 0.125 in
R
V
Human Body Model (Note 2)
Machine Model (Note 3)
ꢃ 2000
ꢃ 200
V
ESD
Charged Device Model (Note 4)
ꢃ 1000
I
Latchup Performance
Above V and Below GND at 85_C (Note 5)
ꢂ
3
0
0
mA
LATCHUP
CC
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. I absolute maximum rating must be observed.
O
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
6. For high frequency or heavy load considerations, see Chapter 2the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
Unit
V
V
DC Supply Voltage
(Referenced to GND)
(Referenced to GND)
6.0
CC
V , V
IN OUT
DC Input Voltage, Output Voltage
V
V
CC
T
Operating Temperature, All Package Types
ꢀ
5
5
ꢁ
1
2
5
_C
ns
A
t , t
r
Input Rise and Fall Time
(Figure 3)
V
V
V
= 2.0 V
= 4.5 V
= 6.0 V
0
0
0
1000
500
400
f
CC
CC
CC
7. Unused inputs may not be left open. All inputs must be tied to a high−logic voltage level or a low−logic input voltage level.
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