MC74AC646, MC74ACT646
V
CC
CBA SBA
G
B
B
B
B
B
B
B
B
7
0
1
2
3
4
5
6
PIN ASSIGNMENT
24 23 22 21 20 19 18 17 16 15
14 13
PIN
A –A
FUNCTION
Data Register Inputs
Data Register A Outputs
0
7
B –B
Data Register B Inputs
Data Register B Outputs
0
7
CAB, CBA
SAB, SBA
DIR, G
Clock Pulse Inputs
1
2
3
4
5
6
7
8
9
10
A
11
12
Transmit/Receive Inputs
Output Enable Inputs
CAB SAB DIR
A
0
A
1
A
2
A
3
A
4
A
5
A
7
GND
6
Figure 5. Pinout: 24–Lead Packages Conductors
(Top View)
A
A
A
B
A
B
A
B
A
B
A
B
A
B
0
1
2
3
4
5
6
7
CAB
SAB
DIR
CBA
SBA
G
B
0
B
1
2
3
4
5
6
7
Figure 6. Logic Symbol
G
DIR
CBA
SBA
CAB
SAB
1 OF 8 CHANNELS
D
0
0
C
B
0
A
0
D
C
0
0
TO 7 OTHER CHANNELS
NOTE: This diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
Figure 7. Logic Diagram
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