MC33260
Th–Stdwn
VCC
5
Current Sense
Comparator
–
+
Synchronization
Arrangement
OVP, UVP
S
Q
PWM
Latch
Output
Buffer
7
ZCD & OCP
R
&
Q
–60 mV
PWM Latch
Comparator
Output_Ctrl
+
Oscillator Sawtooth
–
Vcontrol (Vpin2 – Regulation Output)
Figure 26. PWM Latch
A LEB (Leading Edge Blanking) has been implemented.
This circuitry disconnects the Current Sense comparator
from pin 4 and disables it during the 400 first ns of the power
switch conduction. This prevents the block from reacting on
the current spikes that generally occur at power switch turn
on. Consequently, proper operation does not require any
filtering capacitor on pin 4.
PROTECTIONS
OCP (Overcurrent Protection)
Practically, Vpin1 that is in the range of 2.5 V, can be
neglected. The equation can then be simplified:
V
ovpH
+
Ro<M
W
>
I
ovpH
<
m
A> < V>
On the other hand, the OVP low threshold is:
V
ovpL
+
Vpin1
)
Ro
I
ovpL
where Iovp–L is the internal low OVP current threshold.
Consequently, Vpin1 being neglected:
V
ovpL
Refer to
Current Sense Block.
OVP (Overvoltage Protection)
+
Ro<M
W
>
I
<
m
A> < V>
ovpL
The feedback current (Io) is compared to a threshold
current (IovpH). If it exceeds this value, the gate drive signal
is maintained low until this current gets lower than a second
level (IovpL).
Gate
Drive
Enable
Vcontrol
The OVP hysteresis prevents erratic behavior.
IovpL is guaranteed to be higher than IregH (refer to
parameters specification). This ensures that the OVP
function doesn’t interfere with the regulation one.
UVP (Undervoltage Protection)
Io
Iuvp
IregL IregH IovpL IovpH
This function detects when the feedback current is lower
than 14% of Iref. In this case, the PWM latch is reset and the
power switch is kept off.
This protection is useful to:
•
Protect the preregulator from working in too low
mains conditions.
•
To detect the feedback current absence (in case of a
nonproper connection for instance).
The UVP threshold is:
V uvp
[
Vpin1
)
R o<M
W
>
I uvp<
m
A> (V)
Figure 27. Internal Current Thresholds
Practically (Vpin1 being neglected),
V uvp
So, the OVP upper threshold is:
V
ovpH
+
Vpin1
)
+
Ro<M
W
>
I uvp<
m
A> <V>
Ro
I
ovpH
Maximum On–Time Limitation
where:
Ro is the feedback resistor that is connected between
pin 1 and the output voltage,
Iovp–H is the internal upper OVP current threshold,
Vpin1 is the pin 1 clamp voltage.
As explained in
PWM Latch,
the maximum on–time is
accurately controlled.
Pin Protection
All the pins are ESD protected.
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