MC33171 MC33172 MC33174
APPLICATIONS INFORMATION – CIRCUIT DESCRIPTION/PERFORMANCE FEATURES
Although the bandwidth, slew rate, and settling time of the
voltage to approach within millivolts of VEE. For sink currents
MC33171/72/74 amplifier family is similar to low power op
(> 0.4 mA), diode D3 clamps the voltage across R4. Thus the
amp products utilizing JFET input devices, these amplifiers
negative swing is limited by the saturation voltage of Q15,
offer additional advantages as a result of the PNP transistor
plus the forward diode drop of D3 (≈VEE +1.0 V). Therefore
differential inputs and an all NPN transistor output stage.
an unprecedented peak–to–peak output voltage swing is
Because the input common mode voltage range of this
possible for a given supply voltage as indicated by the output
input stage includes the VEE potential, single supply
swing specifications.
operation is feasible to as low as 3.0 V with the common
If the load resistance is referenced to VCC instead of
mode input voltage at ground potential.
ground for single supply applications, the maximum possible
The input stage also allows differential input voltages up to
output swing can be achieved for a given supply voltage. For
±44
V, provided the maximum input voltage range is not
light load currents, the load resistance will pull the output to
exceeded. Specifically, the input voltages must range
VCC during the positive swing and the output will pull the load
between VCC and VEE supply voltages as shown by the
resistance near ground during the negative swing. The load
maximum rating table. In practice, although
not
resistance value should be much less than that of the
recommended,
the input voltages can exceed the VCC
feedback resistance to maximize pull–up capability.
voltage by approximately 3.0 V and decrease below the VEE
Because the PNP output emitter–follower transistor has
voltage by 0.3 V without causing product damage, although
been eliminated, the MC33171/72/74 family offers a 15 mA
output phase reversal may occur. It is also possible to source
minimum current sink capability, typically to an output voltage
up to 5.0 mA of current from VEE through either inputs’
of (VEE +1.8 V). In single supply applications the output can
clamping diode without damage or latching, but phase
directly source or sink base current from a common emitter
reversal may again occur. If at least one input is within the
NPN transistor for current switching applications.
common mode input voltage range and the other input is
In addition, the all NPN transistor output stage is inherently
within the maximum input voltage range, no phase reversal
faster than PNP types, contributing to the bipolar amplifier’s
will occur. If both inputs exceed the upper common mode
improved gain bandwidth product. The associated high
input voltage limit, the output will be forced to its lowest
frequency low output impedance (200
Ω
typ @ 1.0 MHz)
voltage state.
allows capacitive drive capability from 0 pF to 400 pF without
Since the input capacitance associated with the small
oscillation in the noninverting unity gain configuration. The
geometry input device is substantially lower (0.8 pF) than that
60°C phase margin and 15 dB gain margin, as well as the
of a typical JFET (3.0 pF), the frequency response for a given
general gain and phase characteristics, are virtually
input source resistance is greatly enhanced. This becomes
independent of the source/sink output swing conditions. This
evident in D–to–A current to voltage conversion applications
allows easier system phase compensation, since output
where the feedback resistance can form a pole with the input
swing will not be a phase consideration. The AC
capacitance of the op amp. This input pole creates a 2nd
characteristics of the MC33171/72/74 family also allow
Order system with the single pole op amp and is therefore
excellent active filter capability, especially for low voltage
detrimental to its settling time. In this context, lower input
single supply applications.
capacitance is desirable especially for higher values of
Although the single supply specification is defined at 5.0 V,
feedback resistances (lower current DACs). This input pole
these amplifiers are functional to at least 3.0 V @ 25°C.
can be compensated for by creating a feedback zero with a
However slight changes in parametrics such as bandwidth,
capacitance across the feedback resistance, if necessary, to
slew rate, and DC gain may occur.
reduce overshoot. For 10 kΩ of feedback resistance, the
If power to this integrated circuit is applied in reverse
MC33171/72/74 family can typically settle to within 1/2 LSB
polarity, or if the IC is installed backwards in a socket, large
of 8 bits in 4.2
µs,
and within 1/2 LSB of 12 bits in 4.8
µs
for
unlimited current surges will occur through the device that
a 10 V step. In a standard inverting unity gain fast settling
may result in device destruction.
configuration, the symmetrical slew rate is typically
As usual with most high frequency amplifiers, proper lead
±
2.1 V/µs. In the classic noninverting unity gain
dress, component placement and PC board layout should
configuration the typical output positive slew rate is also
be exercised for optimum frequency performance. For
2.1 V/µs, and the corresponding negative slew rate will
example, long unshielded input or output leads may result in
usually exceed the positive slew rate as a function of the fall
unwanted input/output coupling. In order to preserve the
time of the input waveform.
relatively low input capacitance associated with these
The all NPN output stage, shown in its basic form on the
amplifiers, resistors connected to the inputs should be
equivalent circuit schematic, offers unique advantages over
immediately adjacent to the input pin to minimize additional
the more conventional NPN/PNP transistor Class AB output
stray input capacitance. This not only minimizes the input
stage. A 10 kΩ load resistance can typically swing within 0.8 V
pole for optimum frequency response, but also minimizes
of the positive rail (VCC) and negative rail (VEE), providing a
extraneous “pick up” at this node. Supply decoupling with
28.4 Vpp swing from
±15
V supplies. This large output swing
adequate capacitance immediately adjacent to the supply pin
becomes most noticeable at lower supply voltages.
is also important, particularly over temperature, since many
The positive swing is limited by the saturation voltage of
types of decoupling capacitors exhibit great impedance
the current source transistor Q7, the VBE of the NPN pull–up
changes over temperature.
transistor Q17, and the voltage drop associated with the
The output of any one amplifier is current limited and thus
short circuit resistance, R5. For sink currents less than
protected from a direct short to ground. However, under such
0.4 mA, the negative swing is limited by the saturation
conditions, it is important not to allow the device to exceed
voltage of the pull–down transistor Q15, and the voltage drop
the maximum junction temperature rating. Typically for
±15
V
across R4 and R5. For small valued sink currents, the above
supplies, any one output can be shorted continuously to
voltage drops are negligible, allowing the negative swing
ground without exceeding the maximum temperature rating.
6
MOTOROLA ANALOG IC DEVICE DATA
ONSEMI [ ON SEMICONDUCTOR ]
