MC34071,2,4,A MC33071,2,4,A
Figure 33. Supply Current versus
Supply Voltage
PSR, POWER SUPPLY REJECTION (dB)
9.0
I CC , SUPPLY CURRENT (mA)
8.0
7.0
6.0
TA = 125°C
5.0
4.0
0
5.0
10
15
20
25
VCC, |VEE|, SUPPLY VOLTAGE (V)
TA = –55°C
105
–PSR (∆VEE = +1.5 V)
95
+PSR (∆VCC = +1.5 V)
85
+PSR = 20 Log
∆V
O/ADM
∆V
CC
∆V
O/ADM
∆V
EE
∆V
CC
–
ADM
+
∆V
EE
∆V
O
Figure 34. Power Supply Rejection
versus Temperature
VCC = +15 V
VEE = –15 V
TA = 25°C
75
–PSR = 20 Log
65
–55
–25
0
25
50
75
100
125
TA, AMBIENT TEMPERATURE (°C)
Figure 35. Channel Separation versus Frequency
en , INPUT NOICE VOLTAGE ( nV
√
Hz )
120
CHANNEL SEPARATION (dB)
100
80
60
40
20
0
10
20
30
50
70
100
200
300
f, FREQUENCY (kHz)
VCC = +15 V
VEE = –15 V
TA = 25°C
70
60
50
40
30
20
10
0
10
Figure 36. Input Noise versus Frequency
2.8
VCC = +15 V
VEE = –15 V
VCM = 0
TA = 25°C
Voltage
2.4
2.0
1.6
1.2
Current
0.8
0.4
100
1.0 k
f, FREQUENCY (kHz)
10 k
0
100 k
i n , INPUT NOISE CURRENT (pA
√
Hz )
APPLICATIONS INFORMATION
CIRCUIT DESCRIPTION/PERFORMANCE FEATURES
Although the bandwidth, slew rate, and settling time of the
MC34071 amplifier series are similar to op amp products
utilizing JFET input devices, these amplifiers offer other
additional distinct advantages as a result of the PNP
transistor differential input stage and an all NPN transistor
output stage.
Since the input common mode voltage range of this input
stage includes the VEE potential, single supply operation is
feasible to as low as 3.0 V with the common mode input
voltage at ground potential.
The input stage also allows differential input voltages up
to
±44
V, provided the maximum input voltage range is not
exceeded. Specifically, the input voltages must range
between VEE and VCC supply voltages as shown by the
maximum rating table. In practice, although not
recommended, the input voltages can exceed the VCC
voltage by approximately 3.0 V and decrease below the VEE
voltage by 0.3 V without causing product damage, although
output phase reversal may occur. It is also possible to source
up to approximately 5.0 mA of current from VEE through
either inputs clamping diode without damage or latching,
although phase reversal may again occur.
If one or both inputs exceed the upper common mode
voltage limit, the amplifier output is readily predictable and
may be in a low or high state depending on the existing input
bias conditions.
Since the input capacitance associated with the small
geometry input device is substantially lower (2.5 pF) than
the typical JFET input gate capacitance (5.0 pF), better
frequency response for a given input source resistance can
be achieved using the MC34071 series of amplifiers. This
performance feature becomes evident, for example, in fast
settling D–to–A current to voltage conversion applications
where the feedback resistance can form an input pole with
the input capacitance of the op amp. This input pole creates
a 2nd order system with the single pole op amp and is
therefore detrimental to its settling time. In this context,
lower input capacitance is desirable especially for higher
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