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MC33035DWG 参数 Datasheet PDF下载

MC33035DWG图片预览
型号: MC33035DWG
PDF下载: 下载PDF文件 查看货源
内容描述: 直流无刷电机控制器 [Brushless DC Motor Controller]
分类和应用: 电机控制器
文件页数/大小: 28 页 / 527 K
品牌: ONSEMI [ ONSEMI ]
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MC33035, NCV33035  
Drive Outputs  
of V . A zener clamp should be connected to this input  
CC  
The three top drive outputs (Pins 1, 2, 24) are open  
collector NPN transistors capable of sinking 50 mA with a  
minimum breakdown of 30 V. Interfacing into higher  
voltage applications is easily accomplished with the circuits  
shown in Figures 24 and 25.  
The three totem pole bottom drive outputs (Pins 19, 20,  
21) are particularly suited for direct drive of N−Channel  
MOSFETs or NPN bipolar transistors (Figures 26, 27, 28  
and 29). Each output is capable of sourcing and sinking up  
when driving power MOSFETs in systems where V is  
greater than 20 V so as to prevent rupture of the MOSFET  
gates.  
The control circuitry ground (Pin 16) and current sense  
inverting input (Pin 15) must return on separate paths to the  
central input source ground.  
CC  
Thermal Shutdown  
Internal thermal shutdown circuitry is provided to protect  
the IC in the event the maximum junction temperature is  
exceeded. When activated, typically at 170°C, the IC acts as  
though the Output Enable was grounded.  
to 100 mA. Power for the bottom drives is supplied from V  
C
(Pin 18). This separate supply input allows the designer  
added flexibility in tailoring the drive voltage, independent  
14  
14  
V
M
4
5
2
1
2
V
CC  
Q
2
Rotor  
Position  
Decoder  
Q
1
Q
3
6
POS  
DEC  
1
R
DLY  
3
24  
24  
22  
Load  
UVLO  
17  
18  
V
M
REF  
21  
20  
19  
Reset  
21  
20  
8
7
C
DLY  
Q
4
25 μA  
V
– (I enable R  
IL  
)
ref  
DLY  
t
[ R  
[ R  
C
In  
ǒ
Ǔ
DLY  
DLY DLY  
V
enable – (I enable R  
)
th  
IL  
DLY  
–6  
6.25 – (20 x 10  
R
)
Transistor Q is a common base stage used to level shift from V to the  
1
CC  
DLY  
C
In  
ǒ
Ǔ
high motor voltage, V . The collector diode is required if V is present  
DLY DLY  
M
CC  
–6  
1.4 – (20 x 10  
R
)
while V is low.  
DLY  
M
Figure 23. Timed Delayed Latched  
Over Current Shutdown  
Figure 24. High Voltage Interface with  
NPN Power Transistors  
http://onsemi.com  
13