MC14538B
THEORY OF OPERATION
1
3
4
A
2
B
5
RESET
V
ref 2
C
X
/R
X
V
ref 1
V
ref 1
V
ref 2
V
ref 1
V
ref 2
V
ref 1
V
ref 2
Q
T
1
2
3
T
Positive edge trigger
Negative edge trigger
Positive edge trigger
4
5
T
Positive edge re–trigger (pulse lengthening)
Positive edge re–trigger (pulse lengthening)
Figure 10. Timing Operation
TRIGGER OPERATION
RETRIGGER OPERATION
The block diagram of the MC14538B is shown in
Figure 1, with circuit operation following.
As shown in Figure 1 and 10, before an input trigger
occurs, the monostable is in the quiescent state with the Q
output low, and the timing capacitor C
X
completely charged
to V
DD
. When the trigger input A goes from V
SS
to V
DD
(while inputs B and Reset are held to V
DD
) a valid trigger is
recognized, which turns on comparator C1 and N–channel
transistor N1 . At the same time the output latch is set. With
transistor N1 on, the capacitor C
X
rapidly discharges toward
V
SS
until V
ref1
is reached. At this point the output of
comparator C1 changes state and transistor N1 turns off.
Comparator C1 then turns off while at the same time
comparator C2 turns on. With transistor N1 off, the capacitor
C
X
begins to charge through the timing resistor, R
X
, toward
V
DD
. When the voltage across C
X
equals V
ref 2
, comparator
C2 changes state, causing the output latch to reset (Q goes
low) while at the same time disabling comparator C2 . This
ends at the timing cycle with the monostable in the quiescent
state, waiting for the next trigger.
In the quiescent state, C
X
is fully charged to V
DD
causing
the current through resistor R
X
to be zero. Both comparators
are “off” with total device current due only to reverse
junction leakages. An added feature of the MC14538B is
that the output latch is set via the input trigger without regard
to the capacitor voltage. Thus, propagation delay from
trigger to Q is independent of the value of C
X
, R
X
, or the duty
cycle of the input waveform.
The MC14538B is retriggered if a valid trigger occurs
followed by another valid trigger before the Q output has
returned to the quiescent (zero) state. Any retrigger, after the
timing node voltage at pin 2 or 14 has begun to rise from
V
ref 1
, but has not yet reached V
ref 2
, will cause an increase
in output pulse width T. When a valid retrigger is initiated
, the voltage at C
X
/R
X
will again drop to V
ref 1
before
progressing along the RC charging curve toward V
DD
. The
Q output will remain high until time T, after the last valid
retrigger.
RESET OPERATION
The MC14538B may be reset during the generation of the
output pulse. In the reset mode of operation, an input pulse
on Reset sets the reset latch and causes the capacitor to be
fast charged to V
DD
by turning on transistor P1 . When the
voltage on the capacitor reaches V
ref 2
, the reset latch will
clear, and will then be ready to accept another pulse. It the
Reset input is held low, any trigger inputs that occur will be
inhibited and the Q and Q outputs of the output latch will not
change. Since the Q output is reset when an input low level
is detected on the Reset input, the output pulse T can be made
significantly shorter than the minimum pulse width
specification.
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