MC14093B
Quad 2-Input NAND"
Schmitt Trigger
The MC14093B Schmitt trigger is constructed with MOS
P–channel and N–channel enhancement mode devices in a single
monolithic structure. These devices find primary use where low power
dissipation and/or high noise immunity is desired. The MC14093B
may be used in place of the MC14011B quad 2–input NAND gate for
enhanced noise immunity or to “square up” slowly changing
waveforms.
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MARKING
DIAGRAMS
14
PDIP–14
P SUFFIX
CASE 646
1
14
SOIC–14
D SUFFIX
CASE 751A
1
14
14093B
AWLYWW
MC14093BCP
AWLYYWW
•
Supply Voltage Range = 3.0 Vdc to 18 Vdc
•
Capable of Driving Two Low–Power TTL Loads or One Low–Power
•
•
•
•
Schottky TTL Load Over the Rated Temperature Range
Triple Diode Protection on All Inputs
Pin–for–Pin Compatible with CD4093
Can be Used to Replace MC14011B
Independent Schmitt–Trigger at each Input
MAXIMUM RATINGS
(Voltages Referenced to V
SS
) (Note 2.)
Symbol
V
DD
V
in
, V
out
I
in
, I
out
P
D
T
A
T
stg
T
L
Parameter
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Input or Output Current
(DC or Transient) per Pin
Power Dissipation,
per Package (Note 3.)
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
(8–Second Soldering)
Value
– 0.5 to +18.0
– 0.5 to V
DD
+ 0.5
±
10
500
– 55 to +125
– 65 to +150
260
Unit
V
V
mA
mW
°C
°C
°C
TSSOP–14
DT SUFFIX
CASE 948G
1
14
SOEIAJ–14
F SUFFIX
CASE 965
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
14
093B
ALYW
MC14093B
AWLYWW
ORDERING INFORMATION
Device
MC14093BCP
MC14093BD
MC14093BDR2
MC14093BDT
MC14093BDTEL
MC14093BDTR2
MC14093BF
MC14093BFEL
Package
PDIP–14
SOIC–14
SOIC–14
TSSOP–14
Shipping
2000/Box
2750/Box
2500/Tape & Reel
96/Rail
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/
_
C From 65
_
C To 125
_
C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
(V
in
or V
out
)
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
SS
or V
DD
). Unused outputs must be left open.
v
v
TSSOP–14 2000/Tape & Reel
TSSOP–14 2500/Tape & Reel
SOEIAJ–14
SOEIAJ–14
See Note 1.
See Note 1.
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
©
Semiconductor Components Industries, LLC, 2000
1
March, 2000 – Rev. 3
Publication Order Number:
MC14093B/D
ONSEMI [ ON SEMICONDUCTOR ]
