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MC14069UBCP 参数 Datasheet PDF下载

MC14069UBCP图片预览
型号: MC14069UBCP
PDF下载: 下载PDF文件 查看货源
内容描述: 六反相器 [Hex Inverter]
分类和应用: 逻辑集成电路光电二极管
文件页数/大小: 8 页 / 175 K
品牌: ONSEMI [ ON SEMICONDUCTOR ]
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MC14069UB
Hex Inverter
The MC14069UB hex inverter is constructed with MOS P–channel
and N–channel enhancement mode devices in a single monolithic
structure. These inverters find primary use where low power
dissipation and/or high noise immunity is desired. Each of the six
inverters is a single stage to minimize propagation delays.
http://onsemi.com
MARKING
DIAGRAMS
14
PDIP–14
P SUFFIX
CASE 646
MC14069UBCP
AWLYYWW
1
14
SOIC–14
D SUFFIX
CASE 751A
1
14
TSSOP–14
DT SUFFIX
CASE 948G
1
500
– 55 to +125
– 65 to +150
260
mW
°C
°C
°C
SOEIAJ–14
F SUFFIX
CASE 965
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
14
MC14069U
AWLYWW
14
069U
ALYW
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky TTL Load Over the Rated Temperature Range
Triple Diode Protection on All Inputs
Pin–for–Pin Replacement for CD4069UB
Meets JEDEC UB Specifications
MAXIMUM RATINGS
(Voltages Referenced to V
SS
) (Note 2.)
Symbol
V
DD
V
in
, V
out
I
in
, I
out
P
D
T
A
T
stg
T
L
Parameter
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Input or Output Current
(DC or Transient) per Pin
Power Dissipation,
per Package (Note 3.)
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
(8–Second Soldering)
Value
– 0.5 to +18.0
– 0.5 to V
DD
+ 0.5
±
10
Unit
V
V
mA
14069U
AWLYWW
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/
_
C From 65
_
C To 125
_
C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
(V
in
or V
out
)
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
SS
or V
DD
). Unused outputs must be left open.
ORDERING INFORMATION
Device
MC14069UBCP
MC14069UBD
MC14069UBDR2
MC14069UBDT
Package
PDIP–14
SOIC–14
SOIC–14
TSSOP–14
Shipping
2000/Box
2750/Box
2500/Tape & Reel
96/Rail
v
v
MC14069UBDTEL TSSOP–14 2000/Tape & Reel
MC14069UBDTR2 TSSOP–14 2500/Tape & Reel
MC14069UBF
MC14069UBFEL
SOEIAJ–14
SOEIAJ–14
See Note 1.
See Note 1.
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
©
Semiconductor Components Industries, LLC, 2000
1
March, 2000 – Rev. 3
Publication Order Number:
MC14069UB/D