MC14046B
PHASE COMPARATOR 1
Input Stage
00
11
01
10
XꢀX
PCA
PCB
in
in
PC1
0
1
out
PHASE COMPARATOR 2
Input Stage
XꢀX
00
11
00
00
11
01
10
10
01
01
10
PCA
PCB
in
in
11
3−State
Output Disconnected
PC2
0
0
1
0
out
LD (Lock Detect)
1
Refer to Waveforms in Figure 3.
Figure 1. Phase Comparators State Diagrams
Characteristic
Using Phase Comparator 1
Using Phase Comparator 2
VCO in PLL system adjusts to minimum
No signal on input PCA .
VCO in PLL system adjusts to center
in
frequency (f ).
frequency (f ).
0
min
Phase angle between PCA and PCB .
90° at center frequency (f ), approaching
Always 0_ in lock (positive rising edges).
in
in
0
0_ and 180° at ends of lock range (2f )
L
Locks on harmonics of center frequency.
Signal input noise rejection.
Yes
No
High
Low
Lock frequency range (2f ).
The frequency range of the input signal on which the loop will stay locked if it was
initially in lock; 2f = full VCO frequency range = f – f
L
.
min
L
max
Capture frequency range (2f ).
The frequency range of the input signal on which the loop will lock if it was initially
out of lock.
C
Depends on low−pass filter characteristics
(see Figure 3). f v f
f = f
C L
C
L
Center frequency (f ).
The frequency of VCO , when VCO = 1/2 V
out in DD
0
VCO output frequency (f).
1
f
=
=
(V
(V
input = V
)
SS
min
CO
CO
R (C + 32 pF)
2
1
Note: These equations are intended to be
a design guide. Since calculated component
values may be in error by as much as a
factor of 4, laboratory experimentation may
be required for fixed designs. Part to part
frequency variation with identical passive
components is typically less than 20%.
1
f
+ f
input = V
)
DD
max
min
R (C + 32 pF)
1
1
Where: 10K v R v 1 M
1
10K v R v 1 M
100pF v C v .01 mF
2
1
Figure 2. Design Information
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