MC14001B Series
B−Suffix Series CMOS Gates
MC14001B, MC14011B, MC14023B,
MC14025B, MC14071B, MC14073B,
MC14081B, MC14082B
The B Series logic gates are constructed with P and N channel
enhancement mode devices in a single monolithic structure
(Complementary MOS). Their primary use is where low power
dissipation and/or high noise immunity is desired.
Features
http://onsemi.com
MARKING
DIAGRAMS
14
PDIP−14
P SUFFIX
CASE 646
1
14
SOIC−14
D SUFFIX
CASE 751A
1
14
TSSOP−14
DT SUFFIX
CASE 948G
1
Value
−0.5 to +18.0
−0.5 to V
DD
+ 0.5
±
10
500
−55 to +125
−65 to +150
260
Unit
V
V
mA
mW
°C
°C
°C
Device
MC14001B
MC14011B
MC14023B
MC14025B
MC14071B
MC14073B
MC14081B
MC14082B
xx
A
WL, L
YY, Y
WW, W
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
SOEIAJ−14
F SUFFIX
CASE 965
1
14
MC140xxB
AWLYWW
14
0xxB
ALYW
140xxB
AWLYWW
MC140xxBCP
AWLYYWW
•
Supply Voltage Range = 3.0 Vdc to 18 Vdc
•
All Outputs Buffered
•
Capable of Driving Two Low−power TTL Loads or One Low−power
Schottky TTL Load Over the Rated Temperature Range.
•
Double Diode Protection on All Inputs Except: Triple Diode
Protection on MC14011B and MC14081B
•
Pin−for−Pin Replacements for Corresponding CD4000 Series
B Suffix Devices
•
Pb−Free Packages are Available*
MAXIMUM RATINGS
(Voltages Referenced to V
SS
)
Symbol
V
DD
V
in
, V
out
I
in
, I
out
P
D
T
A
T
stg
T
L
Parameter
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Input or Output Current
(DC or Transient) per Pin
Power Dissipation, per Package
(Note 1)
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
(8−Second Soldering)
DEVICE INFORMATION
Description
Quad 2−Input NOR Gate
Quad 2−Input NAND Gate
Triple 3−Input NAND Gate
Triple 3−Input NOR Gate
Quad 2−Input OR Gate
Triple 3−Input AND Gate
Quad 2−Input AND Gate
Dual 4−Input AND Gate
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
v
(V
in
or V
out
)
v
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V
SS
or V
DD
). Unused outputs must be left open.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2005
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
1
February, 2005 − Rev. 4
Publication Order Number:
MC14001B/D