MC100LVEL05
ORDERING INFORMATION
Device
MC100LVEL05D
MC100LVEL05DG
MC100LVEL05DR2
MC100LVEL05DR2G
MC100LVEL05DT
MC100LVEL05DTG
MC100LVEL05DTR2
MC100LVEL05DTR2G
MC100LVEL05MNR4
MC100LVEL05MNR4G
Package
SOIC−8
SOIC−8
(Pb−Free)
SOIC−8
SOIC−8
(Pb−Free)
TSSOP−8
TSSOP−8
(Pb−Free)
TSSOP−8
TSSOP−8
(Pb−Free)
DFN8
DFN8
(Pb−Free)
Shipping
†
98 Units / Rail
98 Units / Rail
2500 / Tape & Reel
2500 / Tape & Reel
100 Units / Rail
100 Units / Rail
2500 / Tape & Reel
2500 / Tape & Reel
1000 / Tape & Reel
1000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
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ECL Clock Distribution Techniques
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Designing with PECL (ECL at +5.0 V)
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ECLinPSt I/O SPiCE Modeling Kit
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Metastability and the ECLinPS Family
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Interfacing Between LVDS and ECL
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The ECL Translator Guide
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Odd Number Counters Design
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Marking and Date Codes
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Termination of ECL Logic Devices
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Interfacing with ECLinPS
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AC Characteristics of ECL Devices
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