MC10EP142, MC100EP142
3.3 V / 5 V ECL 9−Bit Shift
Register
The MC10EP/100EP142 is a 9−bit shift register, designed with
byte-parity applications in mind. The MC10/100EP142 is capable of
performing serial/parallel data into serial/parallel out and shifting in
only one direction. The nine inputs D0
−
D8 accept parallel input data,
while S−IN accepts serial input data. The QT0:87 outputs do not need
to be terminated for the shift operation to function. To minimize
power, any Q output not used should be left unterminated.
The SEL (Select) input pin is used to switch between the two modes
of operation
−
SHIFT and LOAD. The shift direction is from Bit 0 to
Bit 8. Input data is accepted by the registers a set−up time before the
positive going edge of CLK0 or CLK1; shifting is also accomplished
on the positive clock edge. A HIGH on the Master Reset pin (MR)
asynchronously resets all the registers to zero, overriding CLK0 and
CLK1 inputs.
The 100 Series contains temperature compensation.
Features
http://onsemi.com
MARKING
DIAGRAM*
LQFP−32
FA SUFFIX
CASE 873A
MCxxx
EP142
AWLYYWWG
32
1
1
•
•
•
•
•
•
•
•
•
Shift Frequency >2.8 GHz (Typical)
9-Bit for Byte−Parity Applications
Asynchronous Master Reset
Dual Clocks
PECL Mode Operating Range: V
CC
= 3.0 V to 5.5 V
with V
EE
= 0 V
NECL Mode Operating Range: V
CC
= 0 V
with V
EE
=
−3.0
V to
−5.5
V
Open Input Default State
Safety Clamp on Inputs
Pb−Free Packages are Available
1
32
QFN32
MN SUFFIX
CASE 488AM
MCxxx
EP142
AWLYYWWG
G
xxx
= 10 or 100
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or
G
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
©
Semiconductor Components Industries, LLC, 2006
November, 2006
−
Rev. 16
1
Publication Order Number:
MC10EP142/D
ONSEMI [ ON SEMICONDUCTOR ]
