MC10EL05, MC100EL05
5VꢀECL 2-Input Differential
AND/NAND
The MC10EL/100EL05 is a 2-input differential AND/NAND gate.
The device is functionally equivalent to the E404 device with higher
performance capabilities. With propagation delays and output transition
times significantly faster than the E404, the EL05 is ideally suited for
those applications which require the ultimate in AC performance.
Because a negative 2-input NAND is equivalent to a 2-input OR
function, the differential inputs and outputs of the device allows the EL05
to also be used as a 2-input differential OR/NOR gate.
http://onsemi.com
MARKING
DIAGRAMS*
8
The differential inputs employ clamp circuitry so that under open input
8
1
8
1
conditions (pulled down to V ) the input to the AND gate will be
EE
HEL05
ALYW
G
KEL05
ALYW
G
HIGH. In this way, if one set of inputs is open, the gate will remain active
SOIC−8
D SUFFIX
CASE 751
to the other input.
The 100 Series contains temperature compensation.
1
8
Features
8
8
1
• 275 ps Propagation Delay
1
HL05
ALYWG
G
KL05
• ESD Protection: > 1 kV Human Body Model,
TSSOP−8
DT SUFFIX
CASE 948R
ALYWG
> 100 V Machine Model
G
• PECL Mode Operating Range: V = 4.2 V to 5.7 V with V = 0 V
CC
EE
1
• NECL Mode Operating Range: V = 0 V with V = −4.2 V to −5.7 V
CC
EE
• Internal Input Pulldown Resistors
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity Level 1
DFN8
MN SUFFIX
CASE 506AA
For Additional Information, see Application Note AND8003/D
1
4
1
4
• Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
• Transistor Count = 44 devices
• Pb−Free Packages are Available
L
= Wafer Lot
= Year
= Work Week
= Date Code
= Pb−Free Package
H
K
= MC10
= MC100
Y
W
D
G
4O = MC10
2C = MC100
A
= Assembly Location
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
D
D
1
2
8
7
V
CC
0
0
Q
Q
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
D
D
3
4
6
5
1
1
V
EE
Figure 1. Logic Diagram and Pinout
Assignment
© Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
December, 2006 − Rev. 5
MC10EL05/D
ONSEMI [ ONSEMI ]
