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MC100E111FN 参数 Datasheet PDF下载

MC100E111FN图片预览
型号: MC100E111FN
PDF下载: 下载PDF文件 查看货源
内容描述: 5V ECL 1 : 9差分时钟驱动器 [5V ECL 1:9 Differential Clock Driver]
分类和应用: 时钟驱动器逻辑集成电路输出元件
文件页数/大小: 10 页 / 144 K
品牌: ONSEMI [ ON SEMICONDUCTOR ]
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MC10E111, MC100E111
Table 7. AC CHARACTERISTICS
V
CCx
= 5.0 V; V
EE
= 0.0 V or V
CCx
= 0.0 V; V
EE
=
−5.0
V (Note 13)
−40°C
Symbol
f
MAX
t
PLH
t
PHL
Characteristic
Maximum Toggle Frequency
Propagation Delay to Output
IN (Diff) (Note 14)
IN (SE) (Note 15)
Enable (Note 16)
Disable (Note 16)
Setup Time (Note 17)
Hold Time (Note 18)
Release Time (Note 19)
EN to IN
IN to EN
EN to IN
430
380
400
400
250
50
350
0
−200
100
25
<1
50
250
450
650
75
<2
50
275
375
600
Min
Typ
800
630
680
900
900
430
380
450
450
200
0
300
0
−200
100
25
<1
50
<2
50
275
375
600
Max
Min
25°C
Typ
800
630
680
850
850
430
380
450
450
200
0
300
0
−200
100
25
<1
50
<2
Max
Min
85°C
Typ
800
630
680
850
850
ps
ps
ps
ps
ps
mV
ps
Max
Unit
MHz
ps
t
s
t
H
t
R
t
skew
t
JITTER
V
PP
t
r
, t
f
Within-Device Skew (Note 20)
Random Clock Jitter (RMS)
Minimum Input Swing
Rise/Fall Time
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
13. 10 Series: V
EE
can vary
−0.46
V / +0.06 V.
100 Series: V
EE
can vary
−0.46
/ +0.8 V.
14. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of
the differential output signals.
15. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal.
16. Enable is defined as the propagation delay from the 50% point of a
negative
transition on EN to the 50% point of a
positive
transition
on Q (or a negative transition on Q). Disable is defined as the propagation delay from the 50% point of a
positive
transition on EN to the
50% point of a
negative
transition on Q (or a positive transition on Q).
17. The setup time is the minimum time that EN must be asserted prior to the next transition of IN/IN to prevent an output response greater
than
$75
mV to that IN/IN transition (Figure 3).
18. The hold time is the minimum time that EN must remain asserted after a negative going IN or a positive going IN to prevent an output
response greater than
$75
mV to that IN/IN transition (Figure 4).
19. The release time is the minimum time that EN must be deasserted prior to the next IN/IN transition to ensure an output response that meets
the specified IN to Q propagation delay and output transition times (Figure 5).
20. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device.
IN
IN
t
s
EN
Q
Q
75mV
50%
75mV
IN
IN
t
h
50%
IN
IN
t
r
50%
EN
Q
Q
75mV
EN
Q
Q
75mV
Figure 3. Setup Time
Figure 4. Hold Time
Figure 5. Release Time
http://onsemi.com
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