ADM1024
PIN ASSIGNMENT
Pin No.
1
2
3
4
5
6
7
Mnemonic
NTEST_OUT/ADD
THERM
SDA
SCL
FAN1/AIN1
FAN2/AIN2
CI
Description
Digital I/O. Dual function pin. This is a three−state input that controls the two LSBs of the Serial Bus
Address. This pin functions as an output when doing a NAND test.
Digital I/O. Dual function pin. This pin functions as an interrupt output for temperature interrupts only, or
as an interrupt input for fan control. It has an on−chip 100 kW pullup resistor.
Digital I/O. Serial bus bidirectional data. Open−drain output.
Digital Input. Serial bus clock.
Programmable Analog/Digital Input. 0 V to 2.5 V analog input or digital (0 to V
CC
) amplitude fan
tachometer input.
Programmable Analog/Digital Input. 0 V to 2.5 V analog input or digital (0 to V
CC
) amplitude fan
tachometer input.
Digital I/O. An active high input from an external latch that captures a Chassis Intrusion event. This line
can go high without any clamping action, regardless of the powered state of the ADM1024. The
ADM1024 provides an internal open drain on this line, controlled by Bit 6 of Register 40h or Bit 7 of
Register 46h, to provide a minimum 20 ms pulse on this line to reset the external Chassis Intrusion Latch.
System Ground.
Power (2.8 V to 5.5 V). Typically powered from 3.3 V power rail. Bypass with the parallel combination of
10
mF
(electrolytic or tantalum) and 0.1
mF
(ceramic) bypass capacitors.
Digital Output. Interrupt request (open−drain). The output is enabled when Bit 1 of Register 40h is set
to 1. The default state is disabled. It has an on−chip 100 kW pullup resistor.
Digital Input/Analog Output. An active−high input that enables NAND Test mode board−level connectivity
testing. Refer to the section on NAND testing. Also functions as a programmable analog output when
NAND Test is not selected.
Digital I/O. Master Reset, 5 mA driver (open drain), active low output with a 45 ms minimum pulse width.
Set using Bit 4 in Register 40h. Also acts as reset input when pulled low (e.g., power−on reset). It has an
on−chip 100 kW pullup resistor.
Analog Input. Connected to cathode of first external temperature−sensing diode.
Analog Input. Connected to anode of first external temperature−sensing diode.
Programmable Analog Input. Monitors 12 V supply.
Analog Input. Monitors 5.0 V supply.
Programmable Analog Input. Monitors second processor core voltage or cathode of second external
temperature−sensing diode.
Programmable Analog Input. Monitors 2.5 V supply or anode of second external temperature−sensing
diode.
Analog Input. Monitors first processor core voltage (0 V to 3.6 V).
Digital Input. Core Voltage ID readouts from the processor. This value is read into the VID4 Status
Register. Can also be reconfigured as an interrupt input. It has an on−chip 100 kW pullup resistor.
Digital Input. Core Voltage ID readouts from the processor. This value is read into the VID0–VID3 Status
Register. Can also be reconfigured as an interrupt input. It has an on−chip 100 kW pullup resistor.
Digital Input. Core Voltage ID readouts from the processor. This value is read into the VID0–VID3 Status
Register. Can also be reconfigured as an interrupt input. It has an on−chip 100 kW pullup resistor.
Digital Input. Core Voltage ID readouts from the processor. This value is read into the VID0–VID3 Status
Register. Can also be reconfigured as an interrupt input. It has an on−chip 100 kW pullup resistor.
Digital Input. Core Voltage ID readouts from the processor. This value is read into the VID0–VID3 Status
Register. Can also be reconfigured as an interrupt input. It has an on−chip 100 kW pullup resistor.
8
9
10
11
GND
V
CC
INT
NTEST_IN/AOUT
12
RESET
13
14
15
16
17
18
19
20
21
22
23
24
D1−
D1+
+12 V
IN
+5.0 V
IN
V
CCP2
/D2–
+2.5 V
IN
/D2+
+V
CCP1
VID4/IRQ4
VID3/IRQ3
VID2/IRQ2
VID1/IRQ1
VID0/IRQ0
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