74HC574
AC ELECTRICAL CHARACTERISTICS
(C
L
= 50 pF; Input t
r
= t
f
= 6.0 ns)
Symbol
f
max
Parameter
Maximum Clock Frequency (50% Duty Cycle)
(Figures 3 and 6)
V
CC
(V)
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
60
2.0
3.0
4.5
6.0
Guaranteed Limit
*55
to 25_C
6.0
15
30
35
160
105
32
27
150
100
30
26
140
90
28
24
60
27
12
10
10
15
v85_C
4.8
10
24
28
200
145
40
34
190
125
38
33
175
120
35
30
75
32
15
13
10
15
v125_C
4.0
8.0
20
24
240
190
48
41
225
150
45
38
210
140
42
36
90
36
18
15
10
15
Unit
MHz
t
PLH
,
t
PHL
Maximum Propagation Delay, Clock to Q
(Figures 3 and 6)
ns
t
PLZ
,
t
PHZ
Maximum Propagation Delay, Output Enable to Q
(Figures 4 and 7)
ns
t
PZL
,
t
PZH
Maximum Propagation Delay, Output Enable to Q
(Figures 4 and 7)
ns
t
TLH
,
t
THL
Maximum Output Transition Time, any Output
(Figures 3 and 6)
ns
C
in
C
out
Maximum Input Capacitance
Maximum Three−State Output Capacitance, Output in High−Impedance
State
pF
pF
8. For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High−Speed
CMOS Data Book (DL129/D).
Typical @ 25°C, V
CC
= 5.0 V
C
PD
Power Dissipation Capacitance (Per Enabled Output)*
24
pF
*Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC2
f + I
CC
V
CC
. For load considerations, see the ON
Semiconductor High−Speed CMOS Data Book (DL129/D).
TIMING REQUIREMENTS
(C
L
= 50 pF; Input t
r
= t
f
= 6.0 ns)
Guaranteed Limit
V
CC
Symbol
t
su
Parameter
Minimum Setup Time, Data to Clock
Figure
(V)
2.0
3.0
4.6
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
– 55 to 25_C
Min
50
40
10
9.0
5.0
5.0
5.0
5.0
75
60
15
13
1000
800
500
400
Max
v
85_C
Min
65
50
13
11
5.0
5.0
5.0
5.0
95
80
19
16
1000
800
500
400
Max
v
125_C
Min
75
60
15
13
5.0
5.0
5.0
5.0
110
90
22
19
1000
800
500
400
Max
Unit
ns
t
h
Minimum Hold Time, Clock to Data
ns
t
w
Minimum Pulse Width, Clock
ns
t
r
, t
f
Maximum Input Rise and Fall Times
ns
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