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74HC132DR2G 参数 Datasheet PDF下载

74HC132DR2G图片预览
型号: 74HC132DR2G
PDF下载: 下载PDF文件 查看货源
内容描述: 四2输入与非门施密特触发器输入高性能硅栅CMOS [Quad 2−Input NAND Gate with Schmitt−Trigger Inputs High−Performance Silicon−Gate CMOS]
分类和应用: 触发器
文件页数/大小: 9 页 / 135 K
品牌: ONSEMI [ ON SEMICONDUCTOR ]
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74HC132
Quad 2−Input NAND Gate
with Schmitt−Trigger Inputs
High−Performance Silicon−Gate CMOS
The 74HC132 is identical in pinout to the LS132. The device inputs
are compatible with standard CMOS outputs; with pull−up resistors,
they are compatible with LSTTL outputs.
The HC132 can be used to enhance noise immunity or to square up
slowly changing waveforms.
Features
http://onsemi.com
MARKING
DIAGRAMS
14
SOIC−14
D SUFFIX
CASE 751A
1
HC132G
AWLYWW
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0
mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements as Defined by JEDEC
Standard No. 7A
ESD Performance: HBM
>
2000 V; Machine Model
>
200 V
Chip Complexity: 72 FETs or 18 Equivalent Gates
These are Pb−Free Devices
14
TSSOP−14
DT SUFFIX
CASE 948G
1
HC
132
ALYW
G
G
A1
B1
Y1
A2
B2
Y2
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
B4
A4
Y4
B3
A3
Y3
HC132 = Device Code
A
= Assembly Location
L, WL = Wafer Lot
Y
= Year
W, WW = Work Week
G or
G
= Pb−Free Package
(Note: Microdot may be in either location)
FUNCTION TABLE
Inputs
A
L
L
H
H
B
L
H
L
H
Output
Y
H
H
H
L
Figure 1. Pin Assignment
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
©
Semiconductor Components Industries, LLC, 2007
March, 2007
Rev. 1
1
Publication Order Number:
74HC132/D