74HC02
Quad 2−Input NOR Gate
High−Performance Silicon−Gate CMOS
The 74HC02 is identical in pinout to the LS02. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they
are compatible with LSTTL outputs.
Features
http://onsemi.com
MARKING
DIAGRAMS
14
14
1
SOIC−14
D SUFFIX
CASE 751A
1
HC02G
AWLYWW
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0
mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
•
ESD Performance: HBM
>
2000 V; Machine Model
>
200 V
•
Chip Complexity: 40 FETs or 10 Equivalent Gates
•
These are Pb−Free Devices
LOGIC DIAGRAM
A1
B1
A2
B2
A3
B3
A4
B4
2
3
5
6
8
9
11
12
PIN 14 = V
CC
PIN 7 = GND
1
Y1
14
14
1
TSSOP−14
DT SUFFIX
CASE 948G
1
HC
02
ALYW
G
G
4
Y2
Y=A+B
HC02
= Device Code
A
= Assembly Location
WL or L = Wafer Lot
Y
= Year
WW or W = Work Week
G or
G
= Pb−Free Package
(Note: Microdot may be in either location)
10
Y3
13
Y4
FUNCTION TABLE
Inputs
A
L
L
H
H
B
L
H
L
H
Output
Y
H
L
L
L
PIN ASSIGNMENT
Y1
A1
B1
Y2
A2
B2
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
Y4
B4
A4
Y3
B3
A3
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
©
Semiconductor Components Industries, LLC, 2007
March, 2007
−
Rev. 1
1
Publication Order Number:
74HC02/D
ONSEMI [ ON SEMICONDUCTOR ]
