KAI−04070
Timing Tables
Frame Timing
This timing table is for transferring charge from the photodiodes to the VCCD. See Figures 32 and 33 for frame timing
diagrams.
Table 20. FRAME TIMING
Full Resolution, High Gain or Low Gain
1/4 Resolution, High Gain or Low Gain
1/4 Resolution XLDR
Dual
Dual
Dual
Dual
Dual
Dual
VOUTa
VOUTc
VOUTa
VOUTb
VOUTa
VOUTc
VOUTa
VOUTb
VOUTa
VOUTc
VOUTa
VOUTb
Single
VOUTa
Single
VOUTa
Single
VOUTa
Device
Pin
Quad
Quad
Quad
V1T
V2T
F1T
F2T
F3T
F4T
F1B
F4B
F3B
F2B
F1T
F2T
F3T
F4T
F1B
F4B
F3B
F2B
F1T
F2T
F3T
F4T
F1B
F4B
F3B
F2B
V3T
V4T
V1B
F1B
F2B
F3B
F4B
P1
F1B
F2B
F3B
F4B
P1Q
P1Q
P2Q
P2Q
F1B
F2B
F3B
F4B
V2B
V3B
V4B
H1Sa
H1Ba
H2Sa
H2Ba
Ra
P1XL
P1XL
P2XL
P2XL
RXL
P1
P2
P2
RHG/RLG
P1
RHGQ/RLGQ
P1Q
H1Sb
H1Bb
H2Sb
H2Bb
Rb
P1XL
P1
P2
P2
P1
P2
P1Q
P2Q
P2Q
P1Q
P2Q
P1XL
P2XL
P1XL
P1XL
P2XL
P1XL
P2
P2Q
P2XL
P1
P2
P1
P1Q
P2Q
P1Q
P2XL
RXL
P2XL
RXL
RHG/
RLG
(Note 1)
RHG/
RLG
(Note 1)
RHGQ/
RLGQ
(Note 1)
RHGQ/
RLGQ
(Note 1)
(Note 1)
(Note 1)
R2ab
H1Sc
H1Bc
H2Sc
H2Bc
Rc
R2HG/R2LG
R2HGQ/R2LGQ
R2XL
P1
P1
P2
P2
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
P1Q
P1Q
P2Q
P2Q
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
P1XL
P1XL
P2XL
P2XL
RXL
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
RHG/RLG
P1
RHGQ/RLGQ
P1Q
H1Sd
H1Bd
H2Sd
H2Bd
Rd
P1XL
P1
P2
P1Q
P2Q
P1XL
P2XL
P1XL
P2
P2Q
P2XL
P2
P1
(Note 1)
P2Q
P1Q
(Note 1)
P2XL
RXL
RHG/
RLG
RHGQ/
RLGQ
(Note 1)
R2cd
R2HG/R2LG
(Note 1)
R2HGQ/R2LGQ
(Note 1)
R2XL
(Note 1)
SHP
(Note 2)
SHP1
SHD1
SHPQ
SHDQ
(Note 4)
SHD
(Note 5)
(Note 2)
1. This clock should be held at its high level voltage (0 V) or held at +5.0 V for compatibility with TRUESENSE 5.5 micron Interline Transfer
CCD family of products.
2. SHP and SHD are the sample clocks for the analog front end (AFE) signal processor.
3. This note intentionally left empty.
4. Use SHPLG for the AFE processing the low gain signal. Use SHPHG for the AFE processing the high gain signal.
5. Use SHDLG for the AFE processing the low gain signal. Use SHDHG for the AFE processing the high gain signal.
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