FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC
Data Sheet
The post divider performs several useful functions. First, it allows the VCO to be operated in a narrower range of speeds compared to
the variety of output clock speeds that the device is required to generate. Second, it changes the basic PLL equation to
⎛
N
⎞⎛
1
⎞
f
CLK
=
f
REF
⎜
F
⎟⎜
⎜
N
⎟⎜
N
⎟
⎟
⎝
R
⎠⎝
Px
⎠
The extra integer in the denominator permits more flexibility in the programming of the loop for many applications where frequencies
must be achieved exactly.
Note that a nominal 50/50 duty factor is preserved for selections which have an odd modulus.
4.2 Phase Adjust and Sampling
In line-locked or genlocked applications, it is necessary to know the exact phase relation of the output clock relative to the input clock.
Since the VCO is included within the feedback loop in a simple PLL structure, the VCO output is exactly phase aligned with the input
clock. Every cycle of the input clock equals N
R
/N
F
cycles of the VCO clock.
f
IN
Reference
Divider (N
R
)
Phase
Frequency
Detect
VCO
f
OUT
f
IN
f
OUT
Feedback
Divider (N
F
)
Figure 5: Simple PLL
The addition of a post divider, while adding flexibility, makes the phase relation between the input and output clock unknown because
the post divider is outside the feedback loop.
f
IN
Reference
Divider (N
R
)
Phase
Frequency
Detect
VCO
Post
Divider (N
F
)
f
OUT
f
IN
f
VCO
f
OUT
?
Feedback
Divider (N
F
)
f
VCO
Figure 6: PLL with Post Divider
4.2.1 Clock Gobbler (Phase Adjust)
The clock gobbler circuit takes advantage of the unknown relationship between input and output clocks to permit the adjustment of the
CLKP/CLKN output clock phase relative to the REF input. The clock gobbler circuit removes a VCO clock pulse before the pulse clocks
the post divider. In this way, the phase of the output clock can be slipped until the output phase is aligned with the input clock phase.
To adjust the phase relationship, switch the feedback divider source to the post divider input via the FBKDSRC bit, and toggle the GBL
register bit. The clock gobbler output clock is delayed by one VCO clock period for each transition of the GBL bit from zero to one.
AMI Semiconductor
– Rev. 3.0, Jan. 08
www.amis.com
Specifications subject to change without notice
5
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