BelaSigna 200
2.0 Key Features
2.1 System
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16-bit programmable fixed-point DSP core
Configurable WOLA filterbank coprocessor optimized for filterbank calculations
12-Kword program memory (PRAM)
Two 4-Kword data memories (XRAM and YRAM)
Two 384-word dual-port FIFO memories
Two 128-word dual-port 18-bit memories dedicated to WOLA output results
576-word memory dedicated to WOLA gain values, WOLA windows and other configuration data
Internal oscillator
Operating voltage of 1.8V nominal
Ultra-low power: less than 1mW @ 1.28MHz system clock frequency, 1.8V nominal operating voltage, both processors running
Available in a QFN package; other packages available upon request
2.2 RCore DSP
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Dual-Harvard architecture, 16-bit programmable fixed-point DSP with three execution units
Single-cycle multiply-accumulate (MAC) with 40-bit accumulator
Highly parallel instruction set with powerful addressing modes
Flexible address generation (including modulo addressing) for accessing program memory and data memories, plus control and
configuration registers
Separate system and user stacks with dedicated stack pointers
Fast normalization and de-normalization operations optimized for signal level calculation and block-floating point calculations
Supports time-domain pre- and post-processing of input data stream and frequency-domain processing of WOLA output
Master processor for entire system
2.3 WOLA Filterbank Coprocessor
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Mono and stereo time-frequency transforms providing real or complex data results
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Standard library of overlap-add (OLA) and WOLA filterbank configurations
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Configurable number of frequency bands
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Configurable number of frequency bands
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Configurable oversampling and decimation factors
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Configurable windows
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Low group delay (< 4ms for 16 bands possible)
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Fast real and complex gain application for magnitude and phase processing
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Block floating-point calculations (4-bit exponent, 18-bit mantissa) to achieve high fidelity
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Maximum digital gain of 90dB possible
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High-fidelity time-frequency domain processing
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Low-overhead interaction with the RCore through shared memories, control registers and interrupts
2.4 Input Output Processor (IOP)
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Block-based DMA for all audio data provides automatic management of input and output FIFOs that reduces processor overhead
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Mono (one in, one out), simple stereo (two in, one out), full stereo (two in, two out) and digital mixed (two in, one out) operating
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Interacts with the RCore through interrupts and shared memories
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Normal and smart FIFO audio data accessing schemes available
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