BelaSigna 200
Table 7: Instruction Set Continued
Instruction
Description
Instruction
Description
Load loop counter with 8-bit unsigned
SIMM
LDLC0/1 SIMM
PUSH IMM [,B]
Push IMM on stack
Repeat next instruction n+1 times
(9-bit unsigned)
LDSI A, SIMM
LDSI Rij, SIMM
Load A with signed SIMM
REP n
Load pointer register with unsigned
SIMM
REP Reg
Repeat next instruction Reg+1 times
MLD (Rj), (Ri) [,SQ]
MLD Reg, (Ri) [,SQ]
MODR Rj, Ri
Multiplier load and clear A
Multiplier load and clear A
Pointer register modification
Multiplier load and accumulate
Multiplier load and accumulate
REP (Rij)
RES Reg, Bit
RES (Rij), Bit
RET [B]
Repeat next instruction (Rij)+1 times
Clear bit in register
Clear bit in memory
MPYA (Rj), (Ri) [,SQ]
MPYA Reg, (Ri) [,SQ]
Return from subroutine
Round A with AL
RND A
Multiplier load and accumulate
negative
Multiplier load and accumulate
negative
MPYS (Rj), (Ri) [,SQ]
MPYS Reg, (Ri) [,SQ]
SET Reg, Bit
SET (Rij), Bit
Set bit in register
Set bit in memory
MSET (Rj), (Ri) [,SQ]
MSET Reg, (Ri) [,SQ]
Multiplier load
Multiplier load
SET_IE
SHFT n
Set interrupt enable flag
Shift A by +/- n bits (6-bit signed)
Update A and/or PH | PL with X*Y on
condition
Calculate negative value of A on
condition
MUL [Cond] [,A] [,P]
NEG A [,Cond] [,DW]
SHFT A [,Cond] [,INV]
SLEEP [IE]
Shift A by EXP bits on condition
Sleep
NOP
No operation
SUB A, Reg [,C]
SUB A, (Rij) [,C]
SUB A, DRAM [,B]
SUB A, (Rij)p [,C]
SUB A, Rc [,C]
SUBI A, IMM [,C]
SUSI A, SIMM
SWAP A [,Cond]
TGL Reg, Bit
Subtract register from A
Subtract memory from A
Subtract (DRAM) from A
Subtract program memory from A
Subtract Rc register from A
Subtract IMM from A
OR A, Reg
OR register with AH to AH
OR memory with AH to AH
OR (DRAM) with AH to AH
OR program memory with AH to AH
OR Rc register with AH to AH
OR IMM with AH to AH
OR A, (Rij)
OR A, DRAM [,B]
OR A, (Rij)p
OR A, Rc
ORI A, IMM
ORSI A, SIMM
POP Reg [,B]
POP Rc [,B]
PUSH Reg [,B]
PUSH Rc [,B]
Subtract signed SIMM from A
Swap AH, AL on condition
Toggle bit in register
OR unsigned SIMM with AH to AH
Pop register from stack
Pop Rc register from stack
Push register on stack
TGL (Rij), Bit
Toggle bit in memory
TST Reg, Bit
Test bit in register
Push Rc register on stack
TST (Rij), Bit
Test bit in memory
Table 8: Notation
Symbol
Meaning
Accumulator update
Memory bank selection (X or Y)
Symbol
Meaning
A
B
INV
Inverse shift
P
PH | PL update
Program memory address (16 bits)
C
Carry bit
PRAM
Cond
DRAM
Condition in status register
Rc
Rc register (R0..7, PCFG0..2, PCFG4..6, LC0/1)
Data register (AL, AH, X, Y, ST, PC, PL, PH, EXT0, EXP, AE,
EXT3..EXT7)
Low data (X or Y) memory address (8 bits)
Reg
DW
IE
Double word
Ri / Rj / Rij
SIMM
Pointer to X / Y / either data memory
Short immediate data (10 bits)
Square
Interrupt enable flag
Immediate data (16 bits)
IMM
SQ
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