MR27V1652D
BLOCK DIAGRAM
A-1
X8/X16 Switch
CE
OE
BYTE/V
PP
PGM
CE
OE
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
Row Decoder
Memory Matrix
Address Buffer
1,048,576X16-Bit or 2,097,152X8-Bit
Column Decoder
Multiplexer & Page Data Latch
Output Buffer
D0
D1
D2
D3
D4
D5
D6
D7
D8
D10
D9
D12
D14
D15
D11
D13
In 8-bit output mode, these pins are
three-stated and pin D15 functions
as the A-1 address pin.
FUNCTION TABLE
MODE
READ (16-Bit)
READ (8-Bit)
OUTPUT DISABLE
STAND-BY
PROGRAM
PROGRAM INHIBIT
PROGRAM VERIFY
* : Don't Care
CE
L
L
L
H
L
H
H
OE BYTE/V
PP
L
L
H
*
H
H
L
9.75V
4.0V
H
L
H
L
H
L
3.3V
D
OUT
V
CC
D0 - D7
D8 - D14
D
OUT
Hi-Z
Hi-Z
*
Hi-Z
*
D
IN
Hi-Z
D
OUT
D15/A-1
L/H
3/10