¡ Semiconductor
ML9261/62
AC Characteristics-1
(VDD=4.5 to 5.5V, VDISP=40V, Ta=–40 to +85°C)
Parameter
CLK Pulse Width
DIN Setup Time
Symbol
tW (CLK)
Condition
Min.
80
50
50
50
50
50
50
50
50
80
Max. Unit
150
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
SU (D-CLK)
DIN Hold Time
tH (CLK-D)
SU (CLK-LS)
SU (LS-CLK)
tSU (L-CLK)
tH (CLK-L)
CLK-LS Setup Time
LS-CLK Setup Time
t
t
During normal operation
At display data reset
At display data reset
CLK-LS Hold Time
LS-CHG Setup Time
LS-CL Setup Time
LS Pulse Width
t
SU (LS-CHG)
SU (LS-CL)
W (LS)
tW (CHG)
W (CL)
PD, tPRD
tDLH
t
t
CHG Pulse Width
CL Pulse Width
DOUT Delay time
Driver Output Delay Time
10
10
—
—
—
—
—
—
ms
ms
ns
ms
ms
ms
t
t
50
Load: 30pF
1.0
1.0
1.0
Load: 2.0kW resistance in
parallel with 20pF capacitance
tDHL
tDRHL
tTLH
Driver Output Slew Rate
—
—
5.0
5.0
ms
ms
Load: 2.0kW resistance in
tTHL
parallel with 20pF capacitance
AC Characteristics-2
(VDD=3.0 to 3.6V, VDISP=40V, Ta=–40 to +85°C)
Parameter
CLK Pulse Width
DIN Setup Time
Symbol
Condition
Min.
80
50
50
50
50
50
50
50
50
80
Max. Unit
tW (CLK)
150
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSU (D-CLK)
tH (CLK-D)
DIN Hold Time
CLK-LS Setup Time
LS-CLK Setup Time
t
SU (CLK-LS)
SU (LS-CLK)
tSU (L-CLK)
tH (CLK-L)
t
During normal operation
At display data reset
At display data reset
CLK-LS
LS-CHG Setup Time
LS-CL Setup Time
LS Pulse Width
t
SU (LS-CHG)
SU (LS-CL)
W (LS)
tW (CHG)
W (CL)
PD, tPRD
tDLH
t
t
CHG Pulse Width
CL Pulse Width
DOUT Delay time
Driver Output Delay Time
10
10
—
—
—
—
—
—
ms
ms
ns
ms
ms
ms
t
t
50
Load: 30pF
3.0
3.0
3.0
Load: 2.0kW resistance in
parallel with 20pF capacitance
tDHL
tDRHL
tTLH
Driver Output Slew Rate
—
—
5.0
5.0
ms
ms
Load: 2.0kW resistance in
tTHL
parallel with 20pF capacitance
10/16
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