FEDL9092-01
OKI Semiconductor
ML9092-01/02/03/04
Clock synchronous serial interface timing diagrams
Clock synchronous serial interface input timing
tWCH
– VIH3
– VIL3
CS
tCSU
tSYS
tCHD
tWL
tWH
tr
tf
– VIH3
– VIL3
CP
tDHD
tDSU
– VIH3
– VIL3
DI/O
Clock synchronous serial interface input→output timing
tWCH
– VIH3
– VIL3
CS
tCSU
tCHD
tSYS
tr tWH tf tWL
9th Clock
8th Clock
1st Clock
– VIH3
– VIL3
CP
tDOFF
tDOD
tDHD
tDSU
VOH1
VOL1
VIH3 VIH3
VIL3 VIL3
VOH1
VOL1
DI/O
Hiz
Reset timing
tWRE
RESET
– VIL2
External clock
trE
t
tWEL
WEH tfE
– VIH1
– VIL1
OSC1
tSES
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