FEDL9092-01
OKI Semiconductor
ML9092-01/02/03/04
ML9092-02
Function
Pin
63
Symbol
Type
I
Description
CS
Chip select signal input pin
Shift clock signal input pin. This pin is
connected to the Schmitt circuit internally.
64
65
CP
I
CPU interface
Serial data signal I/O pin. This pin is
connected to the Schmitt circuit internally.
DI/O
I/O
Key scan read and rotary encoder read
READY signal output pin.
66
77
KREQ
OSC1
O
I
Connect external resistors with this pin.
This pin is connected to the Schmitt circuit
internally.
Oscillation
78
OSC2
O
If using an external clock, input it from the
OSC1 pin and leave the OSC2 pin open.
Reset input. Initial settings can be
established by applying a “L” level to this
pin. This pin is connected to the Schmitt
circuit internally.
67
79
RESET
I
I
Control signal
Test input pin. This pin is connected to the
TEST
VSS pin.
Input pins that detect status of key
switches. These pins are connected to the
Schmitt circuit internally.
62–59
58–53
51, 52
C0–C3
R0–R5
A, B
I
O
I
Switch signal
Key switch scan signal output pins
Rotary encoder signal input pins.
These pins are connected to the Schmitt
circuit internally.
Port output
80
50–1
100–91
90–81
76
PA0
O
O
Port A output pin
SEG1–SEG60
LCD segment driver output pins
LCD driver output
COM1–COM10
O
—
—
LCD common driver output pins
Logic power supply pin
GND pin
VDD
VSS
68
Voltage doubler reference voltage input
pin
75
VIN
—
—
Power supply
Pins to connect a capacitor for voltage
doubler
74, 73
VC1+, VS1–
72
71, 69
70
VOUT
V0, V2
NC
—
—
—
Voltage doubler output pin
LCD bias pins
Should be left open.
12/66
OKI [ OKI ELECTRONIC COMPONETS ]
