PEDL9040A-03
¡ Semiconductor
ML9040A-Axx/-Bxx
Data Bus Connected with CPU
The data bus connected with CPU is available either once for 8 bits or twice for 4 bits. This
allows the ML9040A-Axx/-Bxx to be interfaced with either an 8-bit or 4-bit CPU.
(1) When the interface data bus is 8 bits
Data bus DB to DB (8 lines) are all used and data input/output is carried out in one
0
7
step.
(2) When the interface data bus is 4 bits
The 8-bit data input/output is carried out in two steps by using only high-order 4 bits
of data bus DB to DB (4 lines)
4
7
The first time data input/output is made for 4-high order bits (DB to DB ) and the
4
7
second time data input/output is made for low-order 4 bits (DB to DB ). Even when
0
3
the data input/output can be completed through high-order 4 bits, be sure to make
another input/output of low-order 4 bits.
(Example: Busy flag Read).
Sincethedatainput/outputiscarriedoutintwostepsasoneexecution,nonormaldata
transfer is executed from the next input/output if accessed only once.
25/49
OKI [ OKI ELECTRONIC COMPONETS ]
