PEDL9044-03
1
Semiconductor
ML9044-xxA/xxB
RS1
RS0
W
R/
E
Busy
(Internal operation)
No
Busy
DR7
IR7
IR6
IR5
IR4
IR3
IR2
DB7
Busy
ADC6
ADC5
ADC4
ADC3
ADC2
DR6
DR5
DR4
DR3
DR2
DB6
DB5
DB4
DB3
DB2
DB1
DB0
ADC1
ADC0
IR1
IR0
DR1
DR0
Writing In IR
(Instruction
Register)
Reading BF (Busy Flag)
and ADC (Address Counter)
Writing In DR
(Data Register)
Figure 2 8-Bit Data Transfer
RS1
RS0
W
R/
E
Busy
(Internal operation)
DB7
No
Busy
IR7
IR6
IR5
IR4
IR3
ADC3
DR7
DR6
DR3
DR2
Busy
ADC6
ADC5
ADC4
IR2
IR1
IR0
ADC2
ADC1
ADC0
DB6
DB5
DB4
DR5
DR4
DR1
DR0
Writing In IR
(Instruction
Register)
Reading BF (Busy Flag)
and ADC (Address Counter)
Writing In DR
(Data Register)
Figure 3 4-Bit Data Transfer
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