¡ Semiconductor
ML9041
2) Large character patterns (5 ¥ 11 dots) (See Table 3–2.)
(1) A method of writing character patterns to the CGRAM from the CPU
The four CGRAM address bits 0 to 3 select one of the lines constituting a character pattern.
First,setthemodetoincrementordecrementfromtheCPU,andtheninputtheCGRAMaddress.
Write each line of the character pattern code in the CGRAM through DB to DB .
0
7
The data lines DB to DB correspond to the CGRAM data bits 0 to 7, respectively (see Table 3–
0
7
2). Input data “1” represents the ON status of an LCD dot and “0” represents the OFF status.
Since the ADC is automatically incremented or decremented by 1 after the data is written to the
CGRAM, it is not necessary to set the CGRAM address again.
The bottom line of a character pattern (the CGRAM address bits 0 to 3 are all “1”, which means
A in hexadecimal) is a cursor line. The ON/OFF pattern of this line is ORed with the cursor
pattern for displaying on the LCD. Therefore, the pattern data for the cursor position should be
all zeros to display the cursor.
Whereas the data given by the CGRAM data bits 0 to 4 with the CGRAM addresses 0 to A in
hexadecimal (set by the CGRAM address bits 0 to 3) is output as display data to the LCD, the data
givenbytheCGRAMdatabits5to7ortheCGRAMaddressesBtoFinhexadecimalisnot. These
bits can be written and read as a RAM area.
(2) A method of displaying CGRAM character patterns on the LCD
The CGRAM is selected when the higher–order 4 bits of a character code are all zeros. Since bits
0and3ofacharactercodearenotused, thecharacterpattern“b”inTable3–2canbeselectedwith
a character code “00”, “01”, “08” or “09” in hexadecimal.
When the 8–bit character code corresponding to a character pattern in the CGRAM is written to
the DDRAM, the character pattern is displayed in the display position specified by the DDRAM
address. (The DDRAM data bits 1 and 2 correspond to the CGRAM address bits 4 and 5,
respectively.)
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