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ML9041A-01ACVWA 参数 Datasheet PDF下载

ML9041A-01ACVWA图片预览
型号: ML9041A-01ACVWA
PDF下载: 下载PDF文件 查看货源
内容描述: [Dot Matrix LCD Driver, 17 X 100 Dots, CMOS, 10.62 X 2.55 MM, GOLD BUMP, DIE-189]
分类和应用:
文件页数/大小: 64 页 / 651 K
品牌: OKI [ OKI ELECTRONIC COMPONETS ]
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PEDL9041A-02
OKI Semiconductor
ML9041A-xxA/xxB
(GND = 0 V, V
DD
= 2.7 to 5.5 V, Ta = –40 to +85°C)
Parameter
Voltage Multiplier
Input Voltage
Symbol
V
MUL
Note 7
V
DD
= 2.7 V, V
IN
= 0 V
f = 125 kHz
Voltage Multiplier
Output Voltage
V
5OUT
A capacitor for the voltage
multiplier = 1 to 4.7
µF
No load
BE = “H”
V
DD
= 5 V, V
5IN
= –2 V, 1/5 bias,
Contrast data: 1F, No load
V
LCD
MAX
Maximum and
minimum LCD
drive voltages
when internal
variable resistors
are used. Note 8
V
LCD
MIN
V
DD
= 5 V, V
5IN
= –2 V, 1/4 bias,
Contrast data: 1F, No load
V
DD
= 4.1 V, V
5IN
= 0 V, 1/5 bias,
Contrast data: 1F, No load
V
DD
= 3.9 V, V
5IN
= 0 V, 1/4 bias,
Contrast data: 1F, No load
V
DD
= 5 V, V
5IN
= –2 V, 1/5 bias,
Contrast data: 00, No load
V
DD
= 5 V, V
5IN
= –2 V, 1/4 bias,
Contrast data: 00, No load
V
DD
= 4.1 V, V
5IN
= 0 V, 1/5 bias,
Contrast data: 00, No load
V
DD
= 3.9 V, V
5IN
= 0 V, 1/4 bias,
Contrast data: 00, No load
Bias Voltage for
Driving LCD
V
LCD1
V
DD
–V
5
V
LCD2
Note 9
1/4 bias
3.3
7.0
1/5 bias
6.6
6.6
3.8
3.6
4.0
3.6
2.2
1.9
3.3
1/4 bias
3.9
1/5 bias
4.1
Condition
Min.
2.7
Typ.
Max.
3.5
(V
DD
–V
IN
)
×
2
V
(V
DD
–V
IN
)
×
2
V
V
DD
–V
5
4.6
4.2
V
2.8
2.5
7.0
V
V
5
V
DD
–V
5IN
Unit
V
Applicable
pins
V
DD
–V
IN
Note 1:
Applied to the voltage drop occurring between any of the V
DD
, V
1
, V
4
and V
5
pins and any of the
common pins (COM
1
to COM
17
) when the current of 4
µA
flows in or flows out at one common
pin.
Also applied to the voltage drop occurring between any of the V
DD
, V
2
, V
3A
(V
3B
) and V
5
pins and
any of the segment pins (SEG
1
to SEG
100
) when the current of 4
µA
flows in or flows out at one
common pin.
The current of 4
µA
flows out when the output level is V
DD
or flows in when the output level is
V
5
.
Note 2:
Applied to the current flowing into the V
DD
pin when the external clock (f
OSC2
= f
in
= 270 kHz) is
fed to the internal R
f
oscillation or OSC
1
under the following conditions:
V
DD
= 5 V
GND = V
5
= 0 V,
V
1
, V
2
, V
3A
(V
3B
) and V
4
: Open
E, SSR, CSR, and BE: “L” (fixed)
Other input pins: “L” or “H” (fixed)
Other output pins: No load
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