PEDL9041A-02
OKI Semiconductor
ML9041A-xxA/xxB
Arbitrator RAM (ABRAM)
The arbitrator RAM (ABRAM) stores arbitrator display data.
100 dots can be displayed in both 1-line and 2-line display modes. The arbitrator RAM has the addresses
(hexadecimal) from “00” to “1F” and the valid display address area is from 00 to 19 (0H to 13H). The area of 20 to
31 (14H to 1FH) not used for display can be used as a data RAM area for general data. Even if the display is shifted
by instruction, the arbitrator display is not shifted.
A capacity of 8 bits by 32 addresses (= 256 bits) is available for data write.
First set the mode to increment or decrement from the CPU, and then input the ABRAM address.
Write Display-ON data in the ABRAM through DB0 to DB7.
DB0 to DB7 correspond to the ABRAM data bit weights 0 to 7 respectively. Input data “1” represents the ON status
of an LCD dot and “0” represents the OFF status.
Since ADC is automatically incremented or decremented by 1 after the data is written to the ABRAM, it is not
necessary to set the ABRAM address again.
Whereas ABRAM data bit weights 0 to 4 are output as display data to the LCD, the ABRAM data bit weights 5 to
7 are not. These bits can be used as a RAM area.
The cursor or blink is also displayed even when a CGRAM or ABRAM address is set in the ADC. Therefore, the
cursor or blink display should be inhibited while the ADC is holding a CGRAM or ABRAM address.
DB6 DB5 DB4 DB3 DB2 DB1 DB0
MSB
ADC
LSB
Hexadecimal
Hexadecimal
The arbitrator RAM can store a maximum of 100 dots of the arbitrator Display-ON data in units of 5 dots.
The relationship with the LCD display positions is shown below.
Relationship between display-ON
data and segment pins
Configuration of input display data
Input data
5XSn+1
5XSn+5
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
*
*
*
E4 E3 E2 E1 E0
* Don’t Care
E4
E0
Display - ON data
Sn = ABRAM address (0 to 19)
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