PEDL9041A-02
OKI Semiconductor
ML9041A-xxA/xxB
FUNCTIONAL DESCRIPTION
Instruction Register (IR), Data Register (DR), and Expansion Instruction Register (ER)
These registers are selected by setting the level of the Register Selection input pins RS0 and RS1. The DR is
selected when both RS0 and RS1 are “H”. The IR is selected when RS0 is “L” and RS1 is “H”. The ER is selected
when both RS0 and RS1 are “L”. (When RS0 is “H” and RS1 is “L”, the ML9041A is not selected.)
The IR stores an instruction code and sets the address code of the display data RAM (DDRAM) or the character
generator RAM (CGRAM).
The microcontroller (CPU) can write to the IR but cannot read from the IR.
The ER stores a contrast adjusting code and sets the address code of the arbitrator RAM (ABRAM).
The CPU can write to or read from the ER.
The DR stores data to be written in the DDRAM, ABRAM and CGRAM and also stores data read from the
DDRAM, ABRAM and CGRAM.
The data written in the DR by the CPU is automatically written in the DDRAM, ABRAM or CGRAM.
When an address code is written in the IR or ER, the data of the specified address is automatically transferred from
the DDRAM, ABRAM or CGRAM to the DR. The data of the DDRAM, ABRAM and CGRAM can be checked
by allowing the CPU to read the data stored in the DR.
After the CPU writes data in the DR, the data of the next address in the DDRAM, ABRAM or CGRAM is selected
to be ready for the next writing by the CPU. Similarly, after the CPU reads the data in the DR, the data of the next
address in the DDRAM, ABRAM or CGRAM is set in the DR to be ready for the next reading by the CPU.
Writing in or reading from these 3 registers is controlled by changing the status of the R/W (Read/Write) pin.
Table 1 R/W pin status and register operation
W
L
R/
RS0
L
RS1
H
H
H
H
L
Operation
Writing in the IR
H
L
L
Reading the Busy flag (BF) and the address counter (ADC)
Writing in the DR
H
H
L
H
L
Reading from the DR
Writing in the ER
H
L
L
L
Reading the contrast code
H
L
Disabled (Not in a busy state, not performing the writes)
Disabled (Not in a busy state, not performing the reads.
Note data read by the CPU is undefined since the data bus
is high impedance.)
H
H
L
Busy Flag (BF)
The status “1” of the Busy Flag (BF) indicates that the ML9041A is carrying out internal operation.
When the BF is “1”, any new instruction is ignored.
When R/W = “H”, RS0 = “L” and RS1 = “H”, the data in the BF is output to the DB7.
New instructions should be input when the BF is “0”.
When the BF is “1”, the output code of the address counter (ADC) is undefined.
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