PEDL9040A-03
¡ Semiconductor
ML9040A-Axx/-Bxx
Timing Generator Circuit
This circuit is used to generate timing signals to activate internal operations upon receipt
of CPU instruction and also from such internal circuits as the DD RAM, CG RAM, and CG
ROM.
It is designed so that the internal operation caused by accessing from the CPU will not
interfer e with the internal operation caused by LCD driving. Consequently, when data
is written from the CPU to DD RAM, flickering does not occur in a display area other than
the display area where the data is written.
In addition, this circuit generates the transfer signal to MSM5259 for display character
expansion.
Display Data RAM (DD RAM)
This RAM is used to store display data of 8-bit character codes (see Table 2).
DD RAM address corresponds to the display position of the LCD. The correspondence
between the two is described in the following.
DD RAM address (set to ADC) is expressed in hexadecimal notation as shown below:
DB6
DB0
LSB
ADC
MSB
Hexadecimal notation
Hexadecimal notation
(Example)
When DD RAM
address is 2A
L
H
2
L
H
L
H
L
A
(1)Corresponden ce between address and display position in the 1-line display mode
First
digit
2
3
4
5
79 80
4E 4F
Display position
DD RAM address (hex.)
00 01 02 03 04
MSB
LSB
(2)When the ML9040A-Axx/-Bxx alone is used, up to 8 characters can be displayed from
the first to eighth digit.
First
digit
2
3
4
5
6
7
8
00 01 02 03 04 05 06 07
When the display is shifted by instruction, the correspondence between the LCD
display position and the DD RAM address changes as shown below:
First
digit
2
3
4
5
6
7
8
(Display
shifted
to right)
4F 00 01 02 03 04 05 06
First
digit
2
3
4
5
6
7
8
(Display
shifted
to left)
01 02 03 04 05 06 07 08
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