PEDL87V2103DIGEST-01
OKI Semiconductor
ML87V2103
No.
80
81
82
83
Symbol
V
DD
V
SS
N.C.
N.C.
I/O
—
—
—
—
Pad Remarks
IO&CORE
IO&CORE
Pin Description
Power supply 3.3 V
Ground
Unused pin
Unused pin
Output enable input pin
0: data disable
1: data enable
*Set to “1” during normal use.
Unused pin
Unused pin
Unused pin
Unused pin
Test input pin – bit 5 (0: normal operation, 1: test mode)
Power supply 3.3 V
Test input pin – bit 4 (0: normal operation, 1: test mode)
Test input pin – bit 3 (0: normal operation, 1: test mode)
Test input pin – bit 2 (0: normal operation, 1: test mode)
Test input pin – bit 1 (0: normal operation, 1: test mode)
Unused pin
Unused pin
Test input pin – bit 6 (0: normal operation, 1: test mode)
Memory test input pin – bit 2 (0: normal operation, 1: test mode)
SELF REFRESH (0: stop, 1: Normal operation)
Ground
84
OE
I
pull-down 50k
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
N.C.
N.C.
N.C.
N.C.
TEST5
V
DD
TEST4
TEST3
TEST2
TEST1
N.C.
N.C.
TEST6
MTEST
SELF
V
SS
—
—
—
—
I
—
I
I
I
I
—
—
I
I
I
—
pull-down 50k
IO&CORE
pull-down 50k
pull-down 50k
pull-down 50k
pull-down 50k
pull-down 50k
pull-down 50k
pull-down 50k
IO&CORE
Notes: Keep the test mode pins set to 0 or leave them open.
7/14
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