PEDL87V2104DIGEST-01
OKI Semiconductor
ML87V2104
No.
42
43
44
45
46
Symbol
V
DD
DNR
N.C.
SSG
INT
I/O
—
I
—
I
I
Pad Remarks
Pin Description
Power supply 3.3 V
Noise reduction output mode setting pin
0: Normal operation
1: Direct noise reduction mode
Unused pin
Internally generated sync signal mode setting pin
Output system sync signal input/output select setting pin
0: OVS, OHS input mode
1: OVS, OHS internally generated output mode
Output system horizontal sync signal input/output pin
Output system vertical sync signal input/output pin
Data output horizontal reference signal output pin
Ground
Power supply 3.3 V
Chrominance signal output pin – bit 0 (LSB)
Chrominance signal output pin – bit 1
Chrominance signal output pin – bit 2
Chrominance signal output pin – bit 3
Ground
Chrominance signal output pin – bit 4
Chrominance signal output pin – bit 5
Chrominance signal output pin – bit 6
Chrominance signal output pin – bit 7(MSB)
Ground
Output system clock pin
Ground
Luminance signal output pin – bit 0 (LSB)
Luminance signal output pin – bit 1
Luminance signal output pin – bit 2
Luminance signal output pin – bit 3
Power supply 3.3 V
Luminance signal output pin – bit 4
Luminance signal output pin – bit 5
Luminance signal output pin – bit 6
Luminance signal output pin – bit 7 (MSB)
Ground
Unused pin
Unused pin
Unused pin
Unused pin
Unused pin
System reset input pin (0 active)
0: System reset 1: Normal operation
Apply ICLK cycle one and more time during “0” level after VDD
voltage has reached the specified level in System reset operation.
pull-down 50k
pull-down 50k
pull-down 50k
Schmitt(IN)
pull-down 50k
Schmitt(IN)
pull-down 50k
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
OHS
OVS
HREF
V
SS
V
DD
CO0
CO1
CO2
CO3
V
SS
CO4
CO5
CO6
CO7
V
DD
OCLK
V
SS
YO0
YO1
YO2
YO3
VDD
YO4
YO5
YO6
YO7
V
SS
N.C.
N.C.
N.C.
N.C.
N.C.
RESET
I/O
I/O
O
—
—
O
O
O
O
—
O
O
O
O
—
I
—
O
O
O
O
—
O
O
O
O
—
—
—
—
—
—
79
I
5/13
OKI [ OKI ELECTRONIC COMPONETS ]
