FEDL70511LA-03
1
Semiconductor
µPLAT_SIO I/F
Pin Name
UTXD
URXD
Direction
O
I
Internal
Pull Up/Down
—
—
Initial
Value
H
—
Pin
Placement
N2
L3
Description
ML70511LA
Serial data output (Pin shared with GPIO3)
Serial data input (Pin shared with GPIO2)
GPIO I/F
Pin Name
GPIO[15:0]
Direction
I/O
Internal
Pull Up/Down
—
Initial
Value
—
Pin
Placement
[*3]
Description
Parallel I/O data
During initialization: input
JTAG I/F
Pin Name
TDI
TDO
TRST
TMS
TCK
Direction
I
O
I
I
I
Internal
Pull Up/Down
Pull down
—
Pull down
Pull down
Pull down
Initial
Value
—
L
—
—
—
Pin
Placement
H4
H2
C13
B12
B13
Description
Serial data input
Serial data output
Reset pin
Mode setting pin
Serial data clock
PCM I/F
Pin Name
PCMOUT
PCMIN
PCMSYNC
Direction
O
I
I/O
Internal
Pull Up/Down
—
Pull down
Pull down
Initial
Value
L
—
—
Pin
Placement
G2
G4
H3
PCM data input
PCM sync signal (8 kHz),
During initialization: input
(can be switched by an internal register)
PCM clock (64 kHz/128 kHz)
PCMCLK
I/O
Pull down
—
G3
During initialization: input
(can be switched by an internal register)
Description
PCM data output
[*3]
CIO15:
CIO14:
CIO13:
CIO12:
CIO11:
CIO10:
CIO9:
CIO8:
CIO7:
CIO6:
CIO5:
CIO4:
CIO3:
CIO2:
CIO1:
CIO0:
H1
J4
K2
J1
J3
K3
K1
L2
K4
L1
M2
M1
N2
L3
N3
L4
GPIO15/SOUT (UART I/F)
GPIO14/SIN (UART I/F)
GPIO13/DCD (UART I/F)
GPIO12/RTS (UART I/F)
GPIO11/CTS (UART I/F)
GPIO10/DSR (UART I/F)
GPIO9/DTR (UART I/F)
GPIO8/RI (UART I/F)
GPIO7/STXD (SIO I/F)
GPIO6/SRXD (SIO I/F)
GPIO5/STXDCLK (SIIO I/F)
GPIO4/SRXDCLK (SIO I/F)
GPIO3/UTXD (µPLAT_SIO I/F)
GPIO2/URXD (µPLAT_SIO I/F)
GPIO1
GPIO0/VBUS (USB I/F)
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