FEDL7033-02
ML7033
1
Semiconductor
CR13 (SLIC 2 control)
B7
B6
F1_2
0
B5
F0_2
0
B4
SWC2
0
B3
BSEL2
0
B2
E0_2
0
B1
DET2
-
B0
ALM2
-
CR13
default
F2_2
0
* CR13-B1 and B0 are read-only bits. Though either of “0” or “1” will do for these registers when a byte-wide write action is
made, the written values are ignored.
* The INT pin which stays at logic “0” will be released to logic “1” when both of this control register (CR13) and SLIC 1
control register (CR6) are read.
B7 to B5
… Operation mode setting for SLIC2
This 3-bit field determines the output level of the Fn_2 pins. For more detail, refer to Table
6. When any of these bits are cleared, the corresponding Fn_2 pin outputs a logic “0”.
When any of these bits are set, the corresponding Fn_2 pin outputs a logic “1”.
B4
… Uncommitted switch control for SLIC2
0 : switch on
1 : switch off
This bit determines the output level of the SWC2 pin. When this bit is cleared, the SWC2
pin outputs a logic “0”. When this bit is set, the SWC2 pin outputs a logic “1”.
When the SLIC connected to channel 2 is an Intersil RSLICTM series device, the internal
uncommitted switch of the SLIC, located between the SW+ and the SW- pins, can be
controlled by connecting the SWC2 pin directly to the corresponding input pin of the SLIC
device.
B3
B2
… Battery mode select for SLIC2
0 : low battery mode
1 : high battery mode
This bit determines the output level for the BSEL2 pin. When this bit is cleared, the BSEL2
pin outputs a logic “0”. When this bit is set, the BSEL2 pin outputs a logic “1”.
When the SLIC connected to CH2 is an Intersil RSLICTM series device, the battery mode
selection of the SLIC is possible by connecting the BSEL2 pin directly to the corresponding
input pin of the SLIC device.
… Detector mode selection for SLIC2
This bit determines the output level of the E0_2 pin. When this bit is cleared, the E0_2 pin
outputs a logic “0”. When this bit is set, the E0_2 pin outputs a logic “1”.
When the SLIC connected to channel 2 is an Intersil RSLICTM series device, the detector
mode selection of the SLIC is possible by connecting the E0_2 pin directly to the
corresponding input pin of the SLIC device. The event detected by the SLIC is determined
by the F2_2, F1_2, F0_2 and E0_2 output pins as shown in Table 6.
The output level from the E0_2 pin changes 20 µs later (hold timer) in the power-on mode
with the PDN pin = logic “1”, and 200 ns later in the power-down mode with the PDN pin
= logic “0” than a change of this bit value. Refer to Figure 6 for more information.
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