FEDL 7012-04-01
1
Semiconductor
ML7012-04
PIN DESCRIPTIONS
System & Clock
Symbol
OSCO
OSC1
I/O
I
O
Description
Pins to connect crystal, resistors and capacitors for the master clock oscillation. When
supplying the master clock from an external source, use OSC0 and leave OSC1 open.
Master clock frequency = 11.0592 MHz. When
PDN/RST
=
“0”,
OSC1 =
“1”.
Power-down and reset control input pin. When
PDN/RST
=
“0”,
this device is in the
power-down state and internal circuits are reset.
“0”: Power-down state,
“1”:
Normal operation
PDN/RST
After power-on, use this pin after setting it to “0” for 1 µs or more to reset internal
circuits. Waiting for 230 ms or more is required until restarting a normal operation after
reset release.
If this pin remains at “0” after power-on, the internal circuits become undefined and
the power-down current may increase. To avoid this, input
“1”
to this pin and start
oscillation or input the master clock to operate the internal circuits, and then set it to
“0”
I
V.24 Serial Interface
Symbol
STD
SRD
RTS
CTS
DCD
DSR
DTR
CI
I/O
I
O
I
O
O
O
I
O
Description
Send data input pin
Receive data output pin
When
PDN/RST
=
“0”,
SRD outputs
“1”.
RTS (Request to Send) signal input pin
CTS (Clear to Send) signal output pin
When
PDN/RST
=
“0”,
CTS outputs
“1”.
DCD (Data Carrier Detect) signal output pin
When
PDN/RST
=
“0”,
DCD outputs
“1”.
DSR (Data Set Ready) signal output pin
When
PDN/RST
=
“0”,
DSR outputs
“1”.
DTR (Data Terminal Ready) signal input pin
CI (Calling Indicator) signal output pin (*2)
When
PDN/RST
=
“0”,
CI outputs
“1”.
0: Space, 1: Mark
0: Space, 1: Mark
0: On, 1: Off
0: On, 1: Off
0: On, 1: Off
0: On, 1: Off
0: On, 1: Off
0: On, 1: Off
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